Single crystal horizontal access device for vertical three-dimensional (3D) memory and method of forming 3D memory
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have epitaxially grow single crystal silicon to fill the first horizontal opening and house a first source/drain in electrical contact with a conductive material and to form part of an integral, horizontally oriented, conductive digit line. The memory cells also have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain region. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the horizontally oriented digit lines by a dielectric.
1. A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising:
depositing alternating layers of a first dielectric material, a sacrificial material, and a second dielectric material, in repeating iterations vertically to form a vertical stack;
forming a first vertical opening using a first etchant process to expose vertical sidewalls in the vertical stack;
selectively etching a first portion of the sacrificial material in a first region of the vertical stack a first horizontal length back from the first vertical opening to form a first horizontal opening;
epitaxially growing single crystal silicon to fill the first vertical opening and the first horizontal opening;
selectively etching the single crystal silicon to reform the first vertical opening;
selectively etching the second dielectric material to form a second horizontal opening extending a second length back from the first vertical opening; and
gas phase doping a first dopant in a top surface of the single crystal silicon in the first horizontal opening to form a first source/drain region.
2. The method of claim 1 , wherein epitaxially growing the single crystal silicon comprises flowing a disilane (Si 2 H 6 ) gas into the first vertical opening and the first horizontal opening.
3. The method of claim 2 , further comprising flowing the disilane (Si 2 H 6 ) gas into the first vertical opening and the first horizontal opening at a temperature of 600 degree Celsius (° C.) to 1100° C.
4. The method of claim 1 , wherein epitaxially growing the single crystal silicon comprises flowing a silicon based gas into the first vertical opening and the first horizontal opening at a temperature of 600 degree Celsius (° C.) to 1100° C.
5. The method of claim 4 , further comprising flowing a dichlorosilane (SiH 2 Cl 2 ) gas into the first vertical opening and the first horizontal opening at the temperature of 600 degree Celsius (° C.) to 1100° C.
6. The method of claim 1 , wherein forming the first vertical opening further comprises exposing a semiconductor substrate using the first etchant process.
7. The method of claim 6 , wherein the semiconductor substrate formed from a silicon (Si) material.
8. The method of claim 1 , further comprising selectively etching a second portion of the sacrificial material in a second region of the vertical stack to form a storage node of the vertically stacked memory cell before depositing a horizontally oriented access device.
9. The method of claim 8 , further comprising doping a second dopant on a sidewall of the epitaxially grown single crystal silicon to form a second source/drain region before forming the storage node.
10. The method of claim 1 , wherein depositing a conductive material comprises depositing a titanium/titanium nitride (TiN) conductive material, via the first vertical opening, to form a titanium silicide as part of a horizontally oriented digit line to each of the horizontally oriented access devices.
11. A method for forming memory arrays having vertically stacked memory cells and having horizontally oriented access devices with vertically oriented access lines, comprising:
depositing alternating layers of a first dielectric material, a sacrificial material, and a second dielectric material, in repeating iterations vertically through at least four iterations through a vertical stack to form the vertical stack;
forming a first vertical opening to expose a semiconductor substrate and vertical sidewalls in the vertical stack using a first etchant process;
selectively etching the sacrificial material a first horizontal length back from the first vertical opening to form a first horizontal opening having a first height;
epitaxially growing single crystal silicon to fill the first vertical opening and the first horizontal opening by flowing a disilane (Si 2 H 6 ) gas into the first vertical opening and the first horizontal opening;
selectively etching the single crystal silicon to reform the first vertical opening;
selectively etching the second dielectric material, to form a second horizontal opening having a second height and to recess the second dielectric material a second length from the first vertical opening;
gas phase doping a dopant in a top surface of the single crystal silicon to form a first source/drain region;
depositing a conductive material on the first source/drain region below the second dielectric material; and
etching the vertical stack to maintain the first vertical opening and to expose sidewalls, the single crystal silicon, and the first dielectric material to form a body contact.
12. The method of claim 11 , further comprising forming the first vertical opening having a width from 20 to 400 nanometers (nm).
13. The method of claim 11 , further comprising flowing the disilane (Si 2 H 6 ) gas into the first vertical opening and the first horizontal opening at a temperature of 600° C. to 1100° C. to grow the single crystal silicon.
14. The method of claim 11 , further comprising forming the first horizontal opening having a first height from 20 to 150 nanometers (nm).
15. The method of claim 11 , further comprising forming the vertical stack on a complementary metal oxide semiconductor (CMOS).
16. The method of claim 11 , further comprising forming the vertical stack separate from a complementary metal oxide semiconductor (CMOS) and separately bonding the vertical stack to the CMOS.
17. A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising:
forming a first vertical opening using a first etchant process to expose vertical sidewalls in a vertical stack, wherein the vertical stack includes a first dielectric material, a sacrificial material, and a second dielectric material, in repeating iterations;
selectively etching a first portion of the sacrificial material in a first region of the vertical stack a first horizontal length back from the first vertical opening to form a first horizontal opening;
epitaxially growing single crystal silicon to fill the first vertical opening and the first horizontal opening;
selectively etching the single crystal silicon to reform the first vertical opening;
selectively etching the second dielectric material to form a second horizontal opening extending a second length back from the first vertical opening; and
gas phase doping a first dopant in a top surface of the single crystal silicon in the first horizontal opening to form a source/drain region.
18. The method of claim 17 , further comprising etching the vertical stack to maintain the first vertical opening and to expose sidewalls, the single crystal silicon, and the first dielectric material to form a body contact.
19. The method of claim 17 , further comprising depositing a conductive material on the source/drain region below the second dielectric material.
20. The method of claim 17 , further comprising bonding, separately, the vertical stack to a complementary metal oxide semiconductor (CMOS).