Germanium-rich nanowire transistor with relaxed buffer layer
A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body.
1. A semiconductor structure comprising:
a substrate comprising silicon;
a buffer structure on the substrate, the buffer structure comprising a layer of buffer material comprising silicon and germanium with a germanium concentration from 20 to 45 atomic percent and having a lattice constant that is at least 75% relaxed relative to the substrate;
a source and a drain on top of the buffer structure;
a body of monocrystalline semiconductor material extending between the source and the drain, the monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent; and
a gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric between the body and the gate electrode.
2. The semiconductor structure of claim 1 , wherein the body is a nanowire or a nanoribbon.
3. The semiconductor structure of claim 2 , wherein the body is one of a plurality of bodies arranged in a spaced-apart vertical stack.
4. The semiconductor structure of claim 2 , wherein the body has fewer than 1E6 defects per square centimeter.
5. The semiconductor structure of claim 1 , wherein the germanium concentration of the body is from 50 to 85 atomic percent.
6. The semiconductor structure of claim 1 , wherein the layer of buffer structure has a thickness no greater than 300 nm.
7. The semiconductor structure of claim 1 , wherein material of the body has a relaxed lattice constant relative to the substrate and has a strained lattice constant relative to the buffer structure.
8. The semiconductor structure of claim 1 , wherein the substrate contains defects originating at an interface between the substrate and the layer of buffer material, wherein the defects propagate into the substrate.
9. The semiconductor structure of claim 1 , wherein the layer of buffer material is a first layer of buffer material on the substrate and the buffer structure further comprises a second layer of buffer material on the first layer of buffer material, the second layer of buffer material having a higher concentration of germanium than the first layer.
10. The semiconductor structure of claim 1 further comprising isolation material between the buffer structure and a bottom of the source or drain.
11. The semiconductor structure of claim 1 , wherein the source and the drain each comprises (i) silicon, germanium, and tin, (ii) silicon and germanium with at least 50 atomic percent germanium, (iii) an end portion adjacent the gate structure, the end portion comprising from 1-4 atomic percent carbon, or (iv) an end portion adjacent the gate structure, the end portion containing from 85 to 100 atomic percent germanium.
12. A CMOS transistor structure comprising:
a substrate comprising silicon;
a layer of buffer material on the substrate, the buffer material comprising silicon and germanium with germanium from 20 to 45 atomic percent and having a lattice that is at least 75% relaxed with respect to the substrate;
a first source and a first drain on top of the layer of buffer material;
a first body comprising monocrystalline silicon and extending between the first source and the first drain;
a second source and a second drain on top of the layer of buffer material;
a second body extending between the second source and the second drain, the second body comprising silicon and germanium with a germanium concentration from 40 to 85 atomic percent; and
a gate structure wrapped around the first body and around the second body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the first body and the gate electrode and between the second body and the gate electrode.
13. The CMOS transistor structure of claim 12 , wherein the substrate contains defects at an interface with the buffer layer, the defects propagating into the substrate.
14. The CMOS transistor structure of claim 12 , wherein a lattice of the substrate exhibits implant damage.
15. The CMOS transistor structure of claim 12 , wherein material of the first body has a crystal lattice with tensile strain relative to the layer of buffer material and the second body has a crystal lattice with compressive strain relative to the layer of buffer material.
16. The CMOS transistor structure of claim 15 , wherein the first body and the second body each has fewer than 1E6 defects per cm 2 .
17. The CMOS transistor structure of claim 12 , wherein the first body is one of a plurality of first bodies and the second body is one of a plurality of second bodies, the first bodies and the second bodies selected from nanowires, nanoribbons, and nanosheets.
18. The CMOS transistor of claim 12 further comprising isolation material between the layer of buffer material and the first source, between the layer of buffer material and the first drain, between the layer of buffer material and the second source, and between the layer of buffer material and the second drain.
19. A method of fabricating a nanowire transistor, the method comprising:
providing a substrate comprising monocrystalline silicon;
forming on the substrate a layer of buffer material with a thickness less than 200 nm, the layer of buffer material comprising silicon and germanium with germanium from 20 to 45 atomic percent and having a lattice structure that is at least 75% relaxed relative to the substrate;
forming a layer stack over the layer buffer material, the layer stack including alternating layers of a first material comprising silicon and a second material comprising silicon and germanium, wherein the second material contains germanium in an amount from 30 to 85 atomic percent;
etching the layer stack to define one or more fins;
processing each of the one or more fins to include nanowires between a source and a drain; and
forming a gate structure that is wrapped around the nanowires, the gate structure including a gate electrode and a gate dielectric between each of the nanowires and the gate electrode.
20. The method of claim 19 further comprising:
depositing on the layer of buffer material an additional layer of buffer material, the additional layer of buffer material comprising silicon and germanium and having a germanium concentration greater than the layer of buffer material.