Imaging device

1. An imaging device, comprising:

a plurality of pixels in any one of a plurality of semiconductor substrates that is stacked, wherein each of the plurality of pixels is configured to execute photoelectric conversion;

a memory in any one of the plurality of semiconductor substrates, wherein the memory is configured to store a plurality of pieces of image data generated based on a result of the photoelectric conversion;

a memory control unit in any one of the plurality of semiconductor substrates, wherein

the memory control unit is configured to execute a first read operation based on first internal address information, and

the first read operation is executed to read, from the plurality of pieces of the image data stored in the memory, a piece of the image data corresponding to the first internal address information; and

a bus interface in any one of the plurality of semiconductor substrates, wherein the bus interface is configured to:

execute communication for first address information with an external device;

supply the memory control unit with the first internal address information; and

transmit, to the external device, the read piece of the image data corresponding to the first internal address information.

2. The imaging device according to claim 1 , wherein the bus interface is further configured to:

receive the first address information from the external device; and

convert the first address information to the first internal address information.

3. The imaging device according to claim 1 , further comprising a transfer control unit configured to generate the first address information and address information, wherein

the address information corresponds to the first internal address information, and

the bus interface is further configured to:

transmit the first address information to the external device; and

convert the address information to the first internal address information.

4. The imaging device according to claim 1 , wherein

the memory is further configured to store the plurality of pieces of the image data for a plurality of frames of an image, and

an amount of the piece of the image data corresponding to the first internal address information is less than an amount of the image data for one frame of the plurality of frames.

5. The imaging device according to claim 1 , wherein

the bus interface is further configured to supply the memory control unit with a plurality of pieces of the first internal address information, and

the first read operation is for read of the plurality of pieces of the image data for a frame of an image based on the plurality of pieces of the first internal address information.

6. The imaging device according to claim 1 , wherein

the bus interface is further configured to supply the memory control unit with a plurality of pieces of the first internal address information,

the first read operation is for the read of the piece of the image data from the plurality of pieces of the image data for a frame of an image based on a piece of the first internal address information of the plurality of pieces of the first internal address information, and

the piece of the image data corresponds to a partial image of partial images of the frame.

7. The imaging device according to claim 6 , wherein the bus interface is further configured to designate, based on the plurality of pieces of the first internal address information, at least one of a number of the partial images to be read, positions of the partial images in the frame, and sizes of the partial images.

8. The imaging device according to claim 1 , wherein the bus interface is further configured to:

control the execution of the first read operation based on a plurality of pieces of the first internal address information; and

transmit the piece of the image data to the external device based on the control of the execution of the first read operation.

9. The imaging device according to claim 1 , further comprising a signal processing unit configured to execute a signal process of a plurality of signal processes based on the piece of the image data stored in the memory, wherein

the signal process corresponds to the first internal address information, and

the bus interface is further configured to designate, based on the first internal address information, the signal process executed by the signal processing unit.

10. The imaging device according to claim 9 , wherein

an address space that defines the first internal address information includes a plurality of address regions associated with a physical address region of the memory,

each of the plurality of address regions is associated with a respective signal process of the plurality of signal processes,

the signal processing unit is further configured to execute the signal process associated with an address region of the plurality of address regions, and

the first internal address information belongs to the address region.

11. The imaging device according to claim 9 , wherein

the plurality of signal processes includes a first signal process and a second signal process,

the plurality of pieces of the image data includes a plurality of pixel values,

the first signal process is for sequential extraction of first pixel values from the plurality of pixel values in a first order, and

the second signal process is for sequential extraction of second pixel values from the plurality of pixel values in a second order different from the first order.

12. The imaging device according to claim 11 , wherein

the plurality of pixel values corresponds to a plurality of colors,

the first pixel values extracted in the first order correspond to the plurality of colors, and

the second pixel values extracted in the second order correspond to one of the plurality of colors.

13. The imaging device according to claim 9 , wherein

the plurality of signal processes includes a third signal process,

the plurality of pieces of the image data includes a plurality of pixel values, and

the third signal process is for generation of a pixel value of an image based on a specific number of pixel values in the plurality of pixel values.

14. The imaging device according to claim 1 , wherein

the bus interface is further configured to:

execute communication for second address information with the external device;

receive data from the external device; and

supply the memory control unit with second internal address information, and

the memory control unit is further configured to execute, based on the second internal address information, a write operation to write the data in the memory.

15. The imaging device according to claim 14 , wherein

the memory control unit is further configured to execute, based on the first internal address information, a second read operation to read the data stored in the memory, and

the bus interface is further configured to transmit the read data to the external device.

16. The imaging device according to claim 1 , further comprising an image analysis unit configured to execute an image analysis process based on the piece of the image data stored in the memory, wherein

the memory is further configured to store a processing result of the image analysis process,

the memory control unit is further configured to execute, based on the first internal address information, a third read operation to read the processing result stored in the memory, and

the bus interface is further configured to transmit the read processing result to the external device.

17. The imaging device according to claim 1 , further comprising a register, wherein

the bus interface is further configured to:

receive imaging control information from the external device; and

supply the register with register address information,

the register is configured to store the imaging control information based on the register address information, and

each of the plurality of pixels is further configured to execute the photoelectric conversion based on the imaging control information.

18. The imaging device according to claim 1 , wherein

the plurality of pixels is in a first semiconductor substrate of the plurality of semiconductor substrates, and

the memory is in a second semiconductor substrate of the plurality of semiconductor substrates.

19. The imaging device according to claim 18 , wherein

the bus interface is in a third semiconductor substrate of the plurality of semiconductor substrates, and

the first semiconductor substrate, the second semiconductor substrate, and the third semiconductor substrate are stacked in this order.

20. The imaging device according to claim 1 , wherein the memory includes DRAM (Dynamic Random Access Memory).

21. An imaging device, comprising:

a plurality of pixels in any one of a plurality of semiconductor substrates, wherein each of the plurality of pixels is configured to execute photoelectric conversion for a frame of an image;

a memory in any one of the plurality of semiconductor substrates, wherein the memory is configured to store a plurality of pieces of image data generated based on a result of the photoelectric conversion for the frame;

a memory control unit in any one of the plurality of semiconductor substrates, wherein

the memory control unit is configured to execute a read operation based on a piece of internal address information of a plurality of pieces of the internal address information,

the read operation is executed to read, from the plurality of pieces of the image data stored in the memory, a piece of the image data for the frame, and

the piece of the image data corresponds to the piece of the internal address information and a partial image of partial images of the frame; and

a bus interface in any one of the plurality of semiconductor substrates, wherein the bus interface is configured to:

execute communication for address information with an external device;

supply the memory control unit with the plurality of pieces of the internal address information; and

transmit, to the external device, the read piece of the image data corresponding to the piece of the internal address information.