Fully associative cache management
Methods, systems, and devices for fully associative cache management are described. A memory subsystem may receive an access command for storing a first data word in a storage component associated with an address space. The memory subsystem may include a fully associative cache for storing the data words associated with the storage component. The memory subsystem may determine an address within the cache to store the first data word. For example, the memory subsystem may determine an address of the cache indicated by an address pointer (e.g., based on the order of the addresses) and determine a quantity of accesses associated with the data word stored in that cache address. Based on the indicated cache address and the quantity of accesses, the memory subsystem may store the first data word in the indicated cache address or a second cache address sequential to the indicated cache address.
1. A method, comprising:
receiving an access command indicating an address of a storage component;
evicting first data from a first address of a cache based at least in part on the cache failing to include an address of the cache associated with the address of the storage component and based at least in part on a quantity of accesses associated with the first address of the cache failing to satisfy a threshold value;
updating an entry to associate the first address of the cache with the address of the storage component based at least in part on the evicting; and
storing second data associated with the access command at the first address of the cache based at least in part on the updated entry.
2. The method of claim 1 , further comprising:
determining the first address of the cache based at least in part on an address pointer indicating the first address of the cache, wherein the evicting the first data from the first address of the cache is further based at least in part on the determining the first address of the cache.
3. The method of claim 1 , further comprising:
determining that a quantity of accesses associated with a second address of the cache satisfies the threshold value based at least in part on an address pointer indicating the second address of the cache; and
determining the first address of the cache based at least in part on the quantity of accesses associated with the second address of the cache satisfying the threshold value and based at least in part on the first address of the cache being sequential to the second address of the cache according to an order of addresses of the cache, wherein the evicting the first data from the first address of the cache is further based at least in part on the determining the first address of the cache.
4. The method of claim 1 , further comprising:
determining that quantities of accesses associated with a plurality of addresses of the cache satisfy the threshold value based at least in part on an address pointer indicating an initial address of the plurality of addresses of the cache, the plurality of addresses of the cache comprising one or more additional addresses sequential to the initial address of the plurality of addresses of the cache according to an order of addresses of the cache; and
determining the first address of the cache based at least in part on the first address of the cache being sequential to a last address of the plurality of addresses of the cache according to the order of addresses of the cache, wherein the evicting the first data from the first address of the cache is further based at least in part on the determining the first address of the cache.
5. The method of claim 1 , further comprising:
determining a plurality of addresses of the cache based at least in part on an address pointer indicating an initial address of the plurality of addresses of the cache, the plurality of addresses of the cache comprising one or more additional addresses sequential to the initial address of the plurality of addresses of the cache according to an order of addresses of the cache; and
determining the first address of the cache based at least in part on the quantity of accesses associated with the first address of the cache being less than or equal to quantities of accesses associated with other addresses of the plurality of addresses of the cache, wherein the evicting the first data from the first address of the cache is further based at least in part on the determining the first address of the cache.
6. The method of claim 1 , further comprising:
determining that the first data corresponds to valid data for a second address of the storage component and has been updated from corresponding third data stored at the second address of the storage component; and
updating, prior to evicting the first data from the first address of the cache, the second address of the storage component to store the first data based at least in part on the first data corresponding to the valid data and having been updated.
7. The method of claim 6 , wherein the first address of the cache comprises a first field indicating whether the first data is valid data, a second field indicating whether the first data has been updated from the corresponding third data stored at the second address of the storage component, or both.
8. The method of claim 1 , further comprising:
determining that the first data corresponds to invalid data for a second address of the storage component, is the same as third data stored at the second address of the storage component, is corrupted, or any combination thereof; and
refraining from updating the second address of the storage component to store the first data based at least in part on the first data corresponding to the invalid data, the first data being the same as the third data stored at the second address of the storage component, the first data being corrupted, or any combination thereof.
9. The method of claim 8 , wherein the first address of the cache comprises a first field indicating whether the first data is invalid data, a second field indicating whether the first data is the same as the third data stored at the second address of the storage component, a third field indicating whether the first data is corrupted, or any combination thereof.
10. The method of claim 1 , further comprising:
updating an address pointer to indicate a second address of the cache sequential to the first address of the cache according to an order of addresses of the cache based at least in part on the evicting.
11. The method of claim 1 , further comprising:
determining, by one or more content addressable memories, that a set of entries fails to include an entry associating the address of the cache with the address of the storage component, wherein the evicting is based at least in part on the determining, and wherein the entry is updated to associate the first address of the cache with the address of the storage component at the one or more content addressable memories.
12. The method of claim 1 , wherein the first address of the cache comprises a field indicating the quantity of accesses associated with the first address of the cache.
13. An apparatus, comprising:
a cache operable to store a plurality of data words and an indication associated with each data word of the plurality of data words, the indication based at least in part on a quantity of accesses associated with each data word of the plurality of data words; and
a controller coupled with the cache and operable to:
receive an access command indicating an address of a storage component;
evict a first data word from a first address of the cache based at least in part on the cache failing to include an address of the cache associated with the address of the storage component and based at least in part on a first quantity of accesses associated with the first data word failing to satisfy a threshold value;
update an entry to associate the first address of the cache with the address of the storage component based at least in part on the evicting; and
store a second data word associated with the access command at the first address of the cache based at least in part on the updated entry.
14. The apparatus of claim 13 , wherein the controller is further operable to:
determine the first address of the cache based at least in part on an address pointer indicating the first address of the cache, wherein the evicting the first data word from the first address of the cache is further based at least in part on the determining the first address of the cache.
15. The apparatus of claim 13 , wherein the controller is further operable to:
determine that a second quantity of accesses associated with a second address of the cache satisfies the threshold value based at least in part on an address pointer indicating the second address of the cache; and
determine the first address of the cache based at least in part on the second quantity of accesses associated with the second address of the cache satisfying the threshold value and based at least in part on the first address of the cache being sequential to the second address of the cache according to an order of addresses of the cache, wherein the evicting the first data word from the first address of the cache is further based at least in part on the determining the first address of the cache.
16. The apparatus of claim 13 , wherein the controller is further operable to:
determine that quantities of accesses associated with a plurality of addresses of the cache satisfy the threshold value based at least in part on an address pointer indicating an initial address of the plurality of addresses of the cache, the plurality of addresses of the cache comprising one or more additional addresses sequential to the initial address of the plurality of addresses of the cache according to an order of addresses of the cache; and
determine the first address of the cache based at least in part on the first address of the cache being sequential to a last address of the plurality of addresses of the cache according to the order of addresses of the cache, wherein the evicting the first data word from the first address of the cache is further based at least in part on the determining the first address of the cache.
17. The apparatus of claim 13 , wherein the controller is further operable to:
determine a plurality of addresses of the cache based at least in part on an address pointer indicating an initial address of the plurality of addresses of the cache, the plurality of addresses of the cache comprising one or more additional addresses sequential to the initial address of the plurality of addresses of the cache according to an order of addresses of the cache; and
determine the first address of the cache based at least in part on the first quantity of accesses associated with the first address of the cache being less than or equal to quantities of accesses associated with other addresses of the plurality of addresses of the cache, wherein the evicting the first data word from the first address of the cache is further based at least in part on the determining the first address of the cache.
18. The apparatus of claim 13 , wherein the controller is further operable to:
determine that the first data word corresponds to valid data for a second address of the storage component and has been updated from a corresponding third data word stored at the second address of the storage component; and
update, prior to evicting the first data word from the first address of the cache, the second address of the storage component to store the first data word based at least in part on the first data word corresponding to the valid data and having been updated.
19. The apparatus of claim 13 , wherein the controller is further operable to:
determine that the first data word corresponds to invalid data for a second address of the storage component, is the same as a third data word stored at the second address of the storage component, is corrupted, or any combination thereof; and
refrain from updating the second address of the storage component to store the first data word based at least in part on the first data word corresponding to the invalid data, the first data word being the same as the third data word stored at the second address of the storage component, the first data word being corrupted, or any combination thereof.
20. An apparatus, comprising:
a cache configured to be coupled with a storage component,
an interface coupled with the cache and operable to receive, from a host device, a plurality of access commands for storage in the storage component, and
circuitry coupled with the cache and the interface, the circuitry operable to cause the apparatus to:
receive an access command indicating an address of the storage component;
evict first data from a first address of the cache based at least in part on the cache failing to include an address of the cache associated with the address of the storage component and based at least in part on a quantity of accesses associated with the first address of the cache failing to satisfy a threshold value;
update an entry to associate the first address of the cache with the address of the storage component based at least in part on the evicting; and
store second data associated with the access command at the first address of the cache based at least in part on the updated entry.