Select gate maintenance in a memory sub-system

1. A system comprising:

a memory device; and

a processing device, operatively coupled with the memory device, to perform operations comprising:

determining a first error rate associated with a current threshold voltage of at least one select gate device of a block of the memory device; and

responsive to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, adjusting the current threshold voltage to a target threshold voltage.

2. The system of claim 1 , further comprising:

performing an erase operation on the block;

determining a number of program/erase cycles performed on the block;

determining whether the erase operation was performed successfully; and

responsive to determining that erase operation was performed successfully, determining whether the number of program/erase cycles performed on the block satisfies a scan threshold criterion.

3. The system of claim 2 , wherein determining whether the number of program/erase cycles performed on the block satisfies the scan threshold criterion comprises:

determining that the number of program/erase cycles performed on the block is greater than or equal to a threshold number of program/erase cycles; and

determining that the number of program/erase cycles performed on the block is equal to a defined interval for the block.

4. The system of claim 1 , wherein determining the first error rate comprises performing a first threshold voltage integrity scan on the block, and wherein performing the first threshold voltage integrity scan comprises:

causing one or more read voltages to be applied to the at least one select gate device of the block;

receiving one or more output values based on the one or more read voltages; and

comparing the one or more output values to an expected output value based on the target threshold voltage.

5. The system of claim 1 , wherein the processing device to perform further operations comprising:

comparing the first error rate associated with the current threshold voltage of the at least one select gate device to an error rate threshold, wherein the first error rate satisfies the error threshold criterion when the first error rate meets or exceeds the error rate threshold.

6. The system of claim 1 , wherein adjusting the current threshold voltage comprises performing a touch up operation on the at least one select gate device, wherein performing the touch up operation comprises:

iteratively applying a plurality of program pulses to at least one select gate device, the plurality of program pulses to adjust the current threshold voltage to the target threshold voltage; and

verifying, after each iteration, whether the current threshold voltage has reached the target threshold voltage.

7. The system of claim 6 , wherein the processing device to perform further operations comprising:

performing a second threshold voltage integrity scan on the block to determine a second error rate associated with the current threshold voltage of at least one select gate device of the block after performing the touch up operation; and

responsive to the second error rate associated with the current threshold voltage of at least one select gate device after performing the touch up operation not satisfying the error threshold criterion, retiring the block.

8. A method comprising:

determining whether a number of program/erase cycles performed on a block of a memory device satisfies a threshold criterion; and

responsive to the number of program/erase cycles performed on the block satisfying the threshold criterion, adjusting a current threshold voltage of at least one select gate device to a target threshold voltage.

9. The method of claim 8 , further comprising:

detecting an occurrence of a triggering event, wherein detecting the occurrence of the triggering event comprises at least one of receiving a request to erase the block or receiving a request to invalidate the block.

10. The method of claim 8 , further comprising:

responsive to the number of program/erase cycles performed on the block satisfying the threshold criterion, performing a first threshold voltage integrity scan on the block to determine a first error rate associated with the current threshold voltage of at least one select gate device of the block; and

responsive to the first error rate associated with the current threshold voltage of at least one select gate device satisfying an error threshold criterion, performing a touch up operation on at least one select gate device.

11. The method of claim 8 , wherein determining whether the number of program/erase cycles performed on the block satisfies the threshold criterion comprises:

determining whether the number of program/erase cycles performed on the block is greater than or equal to a threshold number of program/erase cycles; and

determining whether the number of program/erase cycles performed on the block is equal to a defined interval for the block.

12. The method of claim 10 , wherein performing the first threshold voltage integrity scan on the block comprises:

applying one or more read voltages to at least one select gate device of the block;

receiving one or more output values based on the one or more read voltages; and

comparing the one or more output values to an expected output value based on the target threshold voltage.

13. The method of claim 10 , wherein performing the touch up operation on at least one select gate device comprises:

iteratively applying a plurality of program pulses to at least one select gate device, the plurality of program pulses to adjust the current threshold voltage to the target threshold voltage; and

verifying, after each iteration, whether the current threshold voltage has reached the target threshold voltage.

14. The method of claim 10 , further comprising:

performing a second threshold voltage integrity scan on the block to determine a second error rate associated with the current threshold voltage of at least one select gate device of the block after performing the touch up operation; and

responsive to the second error rate associated with the current threshold voltage of at least one select gate device after performing the touch up operation not satisfying the error threshold criterion, retiring the block.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

determining a first error rate associated with a current threshold voltage of at least one select gate device of a block of a memory device; and

responsive to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, adjusting the current threshold voltage to a target threshold voltage.

16. The non-transitory computer-readable storage medium of claim 15 , wherein the instructions to cause the processing device to perform further operations comprising:

performing an erase operation on the block;

determining a number of program/erase cycles performed on the block;

determining whether the erase operation was performed successfully; and

responsive to determining that erase operation was performed successfully, determining whether the number of program/erase cycles performed on the block satisfies a scan threshold criterion.

17. The non-transitory computer-readable storage medium of claim 16 , wherein determining whether the number of program/erase cycles performed on the block satisfies the scan threshold criterion comprises:

determining that the number of program/erase cycles performed on the block is greater than or equal to a threshold number of program/erase cycles; and

determining that the number of program/erase cycles performed on the block is equal to a defined interval for the block.

18. The non-transitory computer-readable storage medium of claim 15 , wherein determining the first error rate comprises performing a first threshold voltage integrity scan on the block, and wherein performing the first threshold voltage integrity scan comprises:

causing one or more read voltages to be applied to the at least one select gate device of the block;

receiving one or more output values based on the one or more read voltages; and

comparing the one or more output values to an expected output value based on the target threshold voltage.

19. The non-transitory computer-readable storage medium of claim 15 , wherein adjusting the current threshold voltage comprises performing a touch up operation on the at least one select gate device, wherein performing the touch up operation comprises:

iteratively applying a plurality of program pulses to at least one select gate device, the plurality of program pulses to adjust the current threshold voltage to the target threshold voltage; and

verifying, after each iteration, whether the current threshold voltage has reached the target threshold voltage.

20. The non-transitory computer-readable storage medium of claim 19 , wherein the instructions to cause the processing device to perform further operations comprising:

performing a second threshold voltage integrity scan on the block to determine a second error rate associated with the current threshold voltage of at least one select gate device of the block after performing the touch up operation; and

responsive to the second error rate associated with the current threshold voltage of at least one select gate device after performing the touch up operation not satisfying the error threshold criterion, retiring the block.