Semiconductor device having symmetric conductive interconnection patterns

1. A method for fabricating a semiconductor device, comprising:

forming a stopper layer;

forming an intermediate pattern material layer over the stopper layer;

forming a plurality of first preliminary intermediate patterns by patterning the intermediate pattern material layer;

forming a plurality of second preliminary intermediate patterns by shrinking the first preliminary intermediate patterns;

forming a conductive material layer to cover the second preliminary intermediate patterns;

forming a plurality of preliminary conductive interconnection patterns by patterning the conductive material layer;

forming a filling layer between the preliminary conductive interconnection patterns; and

forming a plurality of intermediate patterns, a plurality of conductive interconnection patterns and a plurality of filling patterns by removing top portions of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns.

2. The method of claim 1 , wherein vertical heights and horizontal widths of the first preliminary intermediate patterns are greater than vertical heights and horizontal widths of the second preliminary intermediate patterns.

3. The method of claim 1 , wherein the conductive interconnection patterns include left conductive interconnection patterns formed on the left of the intermediate patterns and right conductive interconnection patterns formed on the right of the intermediate patterns,

wherein each of the left conductive interconnection patterns includes a flat right side surface and a rounded left side surface, and

each of the right conductive interconnection patterns includes a flat left side surface and a rounded right side surface.

4. The method of claim 3 , wherein each of the intermediate patterns includes both flat side surfaces, and

each of the filling patterns includes both side surfaces that are rounded to have negative slopes where a bottom portion is narrow and a top portion is wide.

5. The method of claim 3 , wherein the sum of a horizontal width of each left conductive interconnection pattern and a horizontal width of each intermediate pattern is equal to a horizontal width of each first preliminary intermediate pattern.

6. The method of claim 3 , wherein the sum of a horizontal width of each right conductive interconnection pattern and a horizontal width of each intermediate pattern is equal to a horizontal width of each first preliminary intermediate pattern.

7. The method of claim 3 , wherein the sum of a horizontal width of each left conductive interconnection pattern and a horizontal width of each right conductive interconnection pattern is equal to a horizontal width of each first preliminary intermediate pattern.

8. The method of claim 1 , wherein the intermediate pattern material layer and the filling layer include at least one of silicon oxide, silicon nitride, or silicon oxynitride, or any combination thereof.

9. The method of claim 1 , wherein the conductive material layer includes a metal.

10. The method of claim 1 , wherein the forming of the preliminary conductive interconnection patterns by patterning the conductive material layer includes performing an etch-back process, and

the plurality of preliminary conductive interconnection patterns are formed by separating the conductive material layer.

11. The method of claim 1 , wherein the removing of a top portion of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns includes performing a Chemical Mechanical Polishing (CMP) process, and

wherein a top surface of each of the intermediate patterns, the conductive interconnection patterns and the filling patterns are coplanar with one another.

12. The method of claim 1 , further comprising:

forming a barrier material layer between the second preliminary intermediate patterns and the conductive material layer; and

forming a plurality of barrier patterns which are physically separate, by patterning the barrier material layer after the forming of the preliminary conductive interconnection patterns.

13. A method for fabricating a semiconductor device, comprising:

forming a lower interlayer dielectric layer over a substrate;

forming a stopper layer over the lower interlayer dielectric layer;

forming first preliminary intermediate patterns over the stopper layer;

forming second preliminary intermediate patterns by shrinking the first preliminary intermediate patterns;

forming preliminary conductive interconnection patterns to cover top surfaces and both side surfaces of the second preliminary intermediate patterns;

forming a filling layer between the preliminary conductive interconnection patterns;

forming intermediate patterns with side surfaces, conductive interconnection patterns on the side surfaces of the intermediate patterns and filling patterns between the conductive interconnection patterns by removing a top portion of each of the filling layer, the preliminary conductive interconnection patterns and the second preliminary intermediate patterns;

forming a capping layer over the intermediate patterns, the conductive interconnection patterns and the filling patterns; and

forming an upper interlayer dielectric layer over the capping layer.

14. The method of claim 13 , wherein the forming of the second preliminary intermediate patterns includes partially removing portions from the top and both sides of the first preliminary intermediate patterns by performing an isotropic etch process on the first preliminary intermediate patterns.

15. The method of claim 13 , wherein the forming of the preliminary conductive interconnection patterns includes:

forming a conductive material layer over the stopper layer to cover top surfaces and side surfaces of the second preliminary intermediate patterns; and

separating the conductive material layer into the preliminary conductive interconnection patterns by performing an etch-back process.

16. The method of claim 13 , wherein top surfaces of the intermediate patterns, the conductive interconnection patterns, and the filling patterns are coplanar with one another.

17. The method of claim 13 , wherein the conductive interconnection patterns include left conductive interconnection patterns formed on the left of the intermediate patterns and right conductive interconnection patterns formed on the right of the intermediate patterns,

wherein each of the left conductive interconnection patterns includes a flat right side surface and a rounded left side surface, and

each of the right conductive interconnection patterns includes a flat left side surface and a rounded right side surface.

18. The method of claim 17 , wherein each of the intermediate patterns includes both flat side surfaces, and

each of the filling patterns includes both side surfaces that are rounded to have negative slopes where a bottom portion is narrow and a top portion is wide.

19. The method of claim 17 , the sum of horizontal width of each left conductive interconnection pattern and horizontal width of each intermediate pattern is equal to a horizontal width of each first preliminary intermediate pattern.

20. The method of claim 17 , wherein the sum of horizontal width of each right conductive interconnection pattern and horizontal width of each intermediate pattern is equal to a horizontal width of each first preliminary intermediate pattern.