Semiconductor device and method for fabricating the same

1. A method for fabricating a semiconductor device, the method comprising:

forming a mold structure including a mold layer and a supporter layer over a semiconductor substrate;

forming an opening penetrating the mold structure;

forming a protective layer on a bottom surface and a sidewall of the opening;

forming a lower electrode over the protective layer;

selectively etching the supporter layer to form a supporter that supports the lower electrode;

removing the mold layer to expose a portion of an outer wall of the protective layer; and

selectively trimming the exposed portion of the protective layer to form a protective layer pattern between the supporter and the lower electrode.

2. The method of claim 1 , wherein the protective layer and the lower electrode include different conductive materials.

3. The method of claim 1 , wherein the protective layer includes an amorphous conductive material.

4. The method of claim 1 , wherein the protective layer includes amorphous niobium or amorphous titanium nitride.

5. The method of claim 1 , wherein the lower electrode includes a polycrystalline conductive material, and the protective layer includes an amorphous conductive material.

6. The method of claim 1 , wherein the lower electrode includes polycrystalline titanium nitride, and the protective layer includes amorphous titanium nitride.

7. The method of claim 1 , wherein the lower electrode includes polycrystalline titanium nitride, and the supporter includes amorphous niobium or amorphous niobium nitride.

8. The method of claim 1 , wherein the lower electrode includes a cylindrical electrode that contacts the protective layer pattern and a pillar-shaped electrode that fills an inside of the cylindrical electrode.

9. The method of claim 8 , wherein the cylindrical electrode includes crystalline titanium nitride, and the pillar-shaped electrode includes polysilicon.

10. The method of claim 1 , wherein the selectively trimming the exposed portion of the protective layer is performed by using a mixture of ammonium hydroxide, hydrogen peroxide, and water.

11. The method of claim 1 , wherein the mold layer includes a multi-level mold layer, and the supporter layer includes a multi-level supporter layer interposed between the multi-level mold layers.

12. The method of claim 1 , wherein the supporter includes a multi-level dielectric supporter, and the protective layer pattern includes a multi-level protective layer pattern positioned between the multi-level dielectric supporter and the lower electrode.

13. The method of claim 1 , wherein the supporter includes silicon nitride or silicon carbon nitride, and the protective layer pattern includes niobium or niobium nitride.

14. The method of claim 1 , wherein the selectively trimming the exposed portion of the protective layer includes:

cutting the exposed portion of the protective layer.

15. The method of claim 1 , wherein the selectively trimming the exposed portion of the protective layer includes:

forming a lower-level protective layer pattern between the bottom portion of the lower electrode and the semiconductor substrate to be vertically spaced apart from the supporter.

16. The method of claim 1 , further comprising, after the selectively trimming the exposed portion of the protective layer:

forming a dielectric layer over the lower electrode, the supporter, and the protective layer pattern; and

forming an upper electrode over the dielectric layer.

17. The method of claim 1 , wherein the selectively trimming the exposed portion of the protective layer includes:

thinning the exposed portion of the protective layer to have a thickness smaller than a thickness of a non-exposed portion of the protective layer to produce a thinned exposed portion.

18. The method of claim 17 , further comprising, after the selectively trimming the exposed portion of the protective layer:

converting the thinned exposed portion into a booster layer;

forming a dielectric layer over the booster layer; and

forming an upper electrode over the dielectric layer.

19. The method of claim 18 , wherein the converting of the thinned exposed portion into the booster layer is performed in an oxygen atmosphere.

20. The method of claim 18 , wherein the converting of the thinned exposed portion into the booster layer includes:

oxidizing the thinned exposed portion in-situ while the dielectric layer is formed.

21. The method of claim 18 , wherein the thinned exposed portion includes niobium, and the booster layer includes niobium oxide.