Semiconductor device structure with hard mask layer over fin structure and method for forming the same

1. A semiconductor device structure, comprising:

a fin structure formed over a substrate;

a hard mask layer formed over the fin structure;

a gate structure formed surrounding the hard mask layer and the fin structure, and a portion of the gate structure is interposed between the fin structure and the hard mask layer;

a source/drain (S/D) structure formed adjacent to the gate structure; and

an inner spacer formed between the gate structure and the S/D structure, wherein the inner spacer is formed along a sidewall of the portion of the gate structure.

2. The semiconductor device structure as claimed in claim 1 , wherein the gate structure further comprises:

a high-k dielectric layer surrounding the hard mask layer and the fin structure; and

a work function layer surrounding the high-k dielectric layer, wherein the hard mask layer and the fin structure are separated by the high-k dielectric layer and the work function layer.

3. The semiconductor device structure as claimed in claim 1 , further comprising:

a contact etch stop layer (CESL) formed over the S/D structure; and

an inter-layer dielectric (ILD) structure formed over the CESL, wherein a sidewall of the hard mask layer is in direct contact with the CESL and the ILD structure.

4. The semiconductor device structure as claimed in claim 1 , wherein sidewalls of the hard mask layer are substantially aligned with sidewalls of the fin structure.

5. The semiconductor device structure as claimed in claim 1 , wherein a thickness of the hard mask layer is substantially the same as a thickness of the fin structure.

6. A semiconductor device structure, comprising:

a plurality of channel structures stacked along a first direction over a substrate;

a gate structure formed over the channel structures, wherein a first portion of the gate structure extends between the plurality of channel structures;

a source/drain (S/D) structure formed adjacent to the gate structure;

a dummy channel layer formed over the channel structures along the first direction, wherein the channel structures is separated from the dummy channel layer by a second portion of the gate structure;

wherein the dummy channel layer is a hard mask layer comprising a dielectric material, and

a contact etch stop layer (CESL) formed adjacent to and in direct contact with the dummy channel layer.

7. The semiconductor device structure as claimed in claim 6 , wherein a thickness of the first portion of the gate structure between the plurality of channel structures is substantially the same as a thickness of the second portion of the gate structure.

8. The semiconductor device structure as claimed in claim 6 , further comprising:

an inner spacer formed between the second portion of the gate structure and the S/D structure, wherein the inner spacer is covered by the dummy channel layer.

9. The semiconductor device structure as claimed in claim 8 , further comprising:

a gate spacer formed over a sidewall of the gate structure, wherein the inner spacer and the gate spacer are separated by a first portion of the dummy channel layer.

10. The semiconductor device structure as claimed in claim 9 , wherein a second portion of the dummy channel layer is directly above the second portion of the gate structure, and a height of the first portion of the dummy channel layer is different from a height of the second portion of the dummy channel layer.

11. The semiconductor device structure as claimed in claim 8 , further comprising:

a gate spacer formed over a sidewall of the gate structure and a sidewall of the dummy channel layer, wherein the gate spacer is in direct contact with the inner spacer.

12. The semiconductor device structure as claimed in claim 6 , wherein a length of the dummy channel layer is substantially the same as a channel length of the semiconductor device structure.

13. The semiconductor device structure as claimed in claim 6 , wherein the dummy channel layer is in direct contact with a topmost surface of the inner spacer.

14. A semiconductor device structure, comprising:

a fin structure formed over a substrate, wherein the fin structure comprises a plurality of nanowires;

a hard mask layer formed over a topmost nanowires of the fin structure;

a gate structure surrounding the nanowires and the hard mask layer; and

a gate spacer layer formed adjacent to the gate structure, wherein the gate spacer layer is formed on and in direct contact with the hard mask layer, wherein a height of a first portion of the hard mask layer directly blow the gate spacer layer is greater than a height of a second portion of the hard mask layer directly below the gate structure.

15. The semiconductor device structure as claimed in claim 14 , further comprising:

an inner spacer layer formed adjacent to the nanowires, wherein a portion of the inner spacer layer is in direct contact with the hard mask layer.

16. The semiconductor device structure as claimed in claim 15 , further comprising:

a source/drain structure formed adjacent to the gate structure, wherein the inner spacer layer is between the gate structure and the source/drain structure.

17. The semiconductor device structure as claimed in claim 16 , further comprising:

a contact etch stop layer (CESL) formed over the source/drain structure; and

a inter-layer dielectric layer formed over the CESL, wherein the hard mask layer is in direct contact with the CESL.

18. The semiconductor device structure as claimed in claim 14 , wherein a thickness of the hard mask layer is substantially the same as a thickness of one of the nanowires.

19. The semiconductor device structure as claimed in claim 14 , wherein a portion of the gate structure is between the nanowires and the hard mask layer.

20. The semiconductor device structure as claimed in claim 14 , wherein a sidewall of the hard mask layer is substantially aligned with a sidewall of one of the nanowires.