Key ladder generating a device public key
A method is provided for generating a key ladder for securely communicating between a first device and a second device using a first device symmetric key and a chip-unique private key. The method includes generating a second processor-specific first device symmetric key from a first processor-specific first device symmetric key and a first identifier (CPU_ID), generating a chip-unique first device application private key (CUAPrK) from a second identifier and the second processor-specific first device symmetric key, generating a chip-unique first device application public key (CUAPuK) from the chip-unique first device application private key (CUAPrK), and transmitting the chip-unique first device application public key (CUAPuK) and an identifier of the processor to the second device.
1. A method of generating a key ladder for securely communicating between a first device and a second device, comprising:
generating, in the first device having a processor, a second processor-specific first device symmetric key from a first processor-specific first device symmetric key and a first identifier;
generating, in the first device, a chip-unique first device application private key from a second identifier and the second processor-specific first device symmetric key; and
generating, in the first device, a chip-unique first device application public key from the chip-unique first device application private key.
2. The method of claim 1 , further comprising providing the chip-unique first device application public key and an identifier of the processor to the second device.
3. The method of claim 1 , further comprising:
generating a certificate signing request file including the chip-unique first device application public key, the first identifier, and a signature corresponding to the chip-unique first device application private key;
submitting the generated certificate signing request file to a certificate authority; and
receiving, in the first device, an application specific device certificate from the certificate authority.
4. The method of claim 1 , wherein the chip-unique first device application private key is generated according to a discrete log-based cryptographic algorithm.
5. The method of claim 4 , wherein the discrete log-based cryptographic algorithm is a Diffie-Hellman, and the chip-unique first device application public key (CUAPuK) is computed as CUAPuK=g CuaPrK mod p, where g is a group generator and p is a prime number of at least 2048 bits.
6. The method of claim 4 , wherein the discrete log-based cryptographic algorithm is one of elliptic curve Diffie-Hellman and elliptic curve digital signature algorithm and the chip-unique first device application public key (CUAPuK) is computed as CUAPuK=CUAPrK*G where G is an elliptic curve base point and the operation * is a elliptic curve multiplication operation.
7. The method of claim 1 , wherein the first processor-specific first device symmetric key is generated by generating the processor-specific first device symmetric key from an identifier of the processor and a chip key.
8. The method of claim 1 , wherein deriving the processor- specific first device symmetric key comprises generating, in the first device, the processor-specific first device symmetric key from a chip private key and a global public key of the second device.
9. The method of claim 8 , further comprising generating, in the first device, a chip public key from the chip private key and providing the chip public key to the second device.
10. The method of claim 9 , wherein the second device generates the chip symmetric key from the global private key and the chip public key, and the method further comprises:
receiving, in the first device, an updated global public key from the second device; and
generating, in the first device an updated processor specific first device symmetric key from a chip private key and the updated public key of the second device.
11. The method of claim 8 , wherein the chip private key is generated by generating, in the first device, the chip private key from a one-time-programmable value of the first device and key parameters.
12. The method of claim 11 , wherein the key parameters are received from the second device.
13. The method of claim 12 , wherein the key parameters specify a public key algorithm for generating the chip private key.
14. The method of claim 1 , further comprising generating, in the first device, a chip-unique first device symmetric key from the processor-specific first device symmetric key and a second application identifier.
15. An apparatus for generating a key ladder for communications between devices, comprising:
a first device, comprising:
a processor;
a memory, communicatively coupled to the processor, the memory storing processor instructions comprising processor instructions for:
generating, in the first device, a second processor-specific first device symmetric key from a first processor-specific first device symmetric key and a first identifier;
generating, in the first device, a chip-unique first device application private key from a second identifier and the second processor-specific first device symmetric key; and
generating, in the first device, a chip-unique first device application public key from the chip-unique first device application private key.
16. The apparatus of claim 15 , wherein the processor instructions further comprise instructions for providing the chip-unique first device application public key and an identifier of the processor to a second device of the plurality of devices.
17. The apparatus of claim 15 , wherein the processor instructions for deriving the processor-specific first device symmetric key comprise processor instructions for generating the processor-specific first device symmetric key from an identifier of the processor and a chip key.
18. The apparatus of claim 15 , wherein the processor instructions for deriving the processor-specific first device symmetric key comprise processor instructions for generating, in the first device, the processor-specific first device symmetric key from a chip private key and a global public key of the second device.
19. The apparatus of claim 18 , wherein the processor instructions further comprise processor instructions for generating, in the first device, a chip public key from the chip private key and providing the chip public key to the second device.
20. The apparatus of claim 19 , wherein the second device generates the chip symmetric key from the global private key and the chip public key, and the processor instructions further comprise instructions for:
receiving, in the first device, an updated global public key from the second device; and
generating, in the first device an updated processor specific first device symmetric key from a chip private key and the updated public key of the second device.