Automatic memory management method, corresponding micro-controller unit and computer program product

1. A computer-implemented method, comprising:

coupling virtual data buffers to respective processing layers of an artificial neural network;

obtaining an ordered visiting sequence of layers of the artificial neural network;

producing, as a function of the ordered visiting sequence of layers, a virtual memory allocation schedule that includes a set of instructions that specify memory allocation operations and memory deallocation operations applicable to the virtual data buffers; and

computing, based on the virtual memory allocation schedule, a physical memory configuration dataset for the artificial neural network, the physical memory configuration dataset comprising sizes and addresses of physical memory locations for the artificial neural network, wherein the method comprises:

initializing a first reference count for a first visited data buffer in the virtual data buffers having an input coupled to a first processing layer in the artificial neural network to a first value equal to a number of processing layers of the artificial neural network having inputs coupled to the first visited data buffer;

generating a memory allocation command for the first visited data buffer having the first reference count initialized;

initializing a second reference count for a second visited data buffer in the virtual data buffers having an input coupled to a second processing layer in the artificial neural network to a second value equal to the number of processing layers of the artificial neural network having inputs coupled to the second visited data buffer;

decrementing the second reference count as a result of visiting one of the processing layers having inputs coupled to the second visited data buffer;

decrementing the first reference count as a result of visiting one of the processing layers having inputs coupled to the first visited data buffer;

determining whether the first reference count or the second reference count equals a value of zero as a result of the decrementing;

deallocating, as a result of determining that the first reference count or the second reference count reached zero, a visited data buffer whose reference count has reached zero; and

iterating the set of sequential operations until an end of the ordered visiting sequence of layers of the artificial neural network is reached.

2. The computer-implemented method of claim 1 , comprising:

configuring data processing circuitry for the artificial neural network according to a directed acyclic graph representing the virtual memory allocation schedule, wherein data buffer nodes in the virtual data buffers are univocally coupled to respective layer processing nodes in the processing layers of the artificial neural network.

3. The computer-implemented method of claim 2 , comprising:

parsing the directed acyclic graph; and

determining dependencies between the processing layers of the artificial neural network.

4. A computer-implemented method, comprising:

coupling virtual data buffers to respective processing layers of an artificial neural network;

obtaining an ordered visiting sequence of layers of the artificial neural network;

producing, as a function of the ordered visiting sequence of layers, a virtual memory allocation schedule that includes a set of instructions that specify memory allocation operations and memory deallocation operations applicable to the virtual data buffers; and

computing, based on the virtual memory allocation schedule, a physical memory configuration dataset for the artificial neural network, the physical memory configuration dataset comprising sizes and addresses of physical memory locations for the artificial neural network, wherein the method comprises:

initializing a list of memory intervals comprising a set of tuples including values indicative of a base physical memory address and of a maximum heap size; and

sequentially parsing the set of instructions included in the virtual memory allocation schedule;

as a result of parsing an instruction in the set of instructions to allocate a first data buffer:

determining, in the list of memory intervals, a temporary memory interval having a smallest size sufficient to store the first data buffer;

allocating the first data buffer in the temporary memory interval; and

updating the list of memory intervals to indicate the temporary memory interval as allocated; and

as a result of parsing an instruction in the set of instructions to deallocate a second data buffer:

deallocating the second data buffer from memory;

merging a memory interval freed as a result of deallocating the second data buffer with one or more free memory intervals in the list of memory intervals; and

updating the list of memory intervals to indicate the memory interval freed,

wherein the physical memory configuration dataset is calculated in connection with parsing the set of instructions.

5. The computer-implemented method of claim 4 , comprising:

initializing a first reference count for a first visited data buffer in the virtual data buffers having an input coupled to a first processing layer in the artificial neural network to a first value equal to a number of processing layers of the artificial neural network having inputs coupled to the first visited data buffer;

generating a memory allocation command for the first visited data buffer having the first reference count initialized;

initializing a second reference count for a second visited data buffer in the virtual data buffers having an input coupled to a second processing layer in the artificial neural network to a second value equal to the number of processing layers of the artificial neural network having inputs coupled to the second visited data buffer;

decrementing the second reference count as a result of visiting one of the processing layers having inputs coupled to the second visited data buffer;

decrementing the first reference count as a result of visiting one of the processing layers having inputs coupled to the first visited data buffer;

determining whether the first reference count or the second reference count equals a value of zero as a result of the decrementing;

deallocating, as a result of determining that the first reference count or the second reference count reached zero, a visited data buffer whose reference count has reached zero; and

iterating the set of sequential operations until an end of the ordered visiting sequence of layers of the artificial neural network is reached.

6. The computer-implemented method of claim 4 , comprising:

tracking each data buffer allocated based on a set of slots referencing one or more memory intervals in the list of memory intervals that store a data buffer name, a starting memory address, and a data buffer size of the data buffer allocated.

7. The computer-implemented method of claim 6 , comprising:

as a result of parsing the instruction to allocate the first data buffer, executing a first pipeline of operations that include:

determining whether the set of slots include an available slot;

appending a new slot to the set of slots as a result of determining that no slots are available, the new slot being empty;

computing a size of an empty slot in the set of slots based on a difference between an address of a next slot subsequent to the empty slot and an address of a previous slot to the empty slot added to a size of the previous slot;

comparing the size of the empty slot with a size of the first data buffer; and

finding a smallest slot of the set of slots in which the first data buffer fits;

as a result of parsing the instruction to deallocate the second data buffer, executing a second pipeline of operations that include:

assigning an empty value to a slot containing the second data buffer;

appending a coordinate of the slot in the physical memory configuration dataset;

as a result of detecting a pair of consecutive empty slots in the set of slots, merging the pair of consecutive empty slots into a single empty slot; and

as a result of parsing a last instruction in the set of instructions:

removing a third slot at an end of the list of memory intervals if the third slot is empty; and

providing, to a processing circuit, the physical allocation configuration dataset that includes memory location addresses of data buffers for implementing the artificial neural network.

8. The computer-implemented method of claim 7 , comprising:

as a result of the first data buffer size being greater than the size of the empty slot, shifting one or more slots subsequent to the empty slot and allocating the first data buffer to the empty slot; and

as a result of the empty slot and the buffer having a same size, allocating the buffer; and

as a result of the size of the first data buffer being smaller than the size of the empty slot, introducing a new empty slot between the empty slot and the next slot.

9. The computer-implemented method of claim 8 , comprising:

computing a difference between the size of the first data buffer and the size of the empty slot as δ=s i −S i ; and

computing a set of slot coordinates as a result of adding the difference to an address of a subsequent non-empty slot, wherein shifting the one or more slots is based on the set of slot coordinates.

10. A system, comprising:

memory; and

processing circuitry coupled to the memory, the processing circuitry configured to:

couple virtual data buffers to respective processing layers of an artificial neural network;

obtain an ordered visiting sequence of layers of the artificial neural network;

produce, as a function of the ordered visiting sequence of layers, a virtual memory allocation schedule that includes a set of instructions that specify memory allocation operations and memory deallocation operations applicable to the virtual data buffers; and

compute, based on the virtual memory allocation schedule, a physical memory configuration dataset for the artificial neural network, the physical memory configuration dataset comprising sizes and addresses of physical memory locations of the artificial neural network, wherein the processing circuitry is configured to:

initialize a list of memory intervals that includes a set of tuples having values indicative of a base physical memory address and of a maximum heap size; and

sequentially parse the set of instructions included in the virtual memory allocation schedule, wherein

for an instruction parsed in the set of instructions to allocate a first data buffer, allocate the first data buffer to a temporary memory interval having a smallest size sufficient to store the first data buffer;

for an instruction parsed in the set of instructions to deallocate a second data buffer, deallocate the second data buffer from memory; and

merge a memory interval freed as a result of deallocating the second data buffer with one or more free memory intervals in the list of memory intervals; and

update the list of memory intervals based on allocation or deallocation of data buffers specified in the set of instructions, the physical memory configuration dataset is calculated in connection with parsing the set of instructions.

11. The system of claim 10 , wherein the processing circuitry is configured according to a directed acyclic graph representing the virtual memory allocation schedule, wherein virtual data buffer nodes are coupled to respective layer processing nodes in the processing layers of the artificial neural network.

12. The system of claim 11 , wherein the processing circuitry is configured to:

parse the directed acyclic graph; and

determine dependencies between the processing layers of the artificial neural network.

13. The system of claim 10 , wherein the processing circuitry is configured to:

track each data buffer allocated based on a set of slots referencing one or more memory intervals in the list of memory intervals that store a data buffer name, a starting memory address, and a data buffer size of the data buffer allocated.

14. A system, comprising:

memory; and

processing circuitry coupled to the memory, the processing circuitry configured to:

couple virtual data buffers to respective processing layers of an artificial neural network;

obtain an ordered visiting sequence of layers of the artificial neural network;

produce, as a function of the ordered visiting sequence of layers, a virtual memory allocation schedule that includes a set of instructions that specify memory allocation operations and memory deallocation operations applicable to the virtual data buffers; and

compute, based on the virtual memory allocation schedule, a physical memory configuration dataset for the artificial neural network, the physical memory configuration dataset comprising sizes and addresses of physical memory locations of the artificial neural network, wherein the processing circuitry is configured to:

initialize a first reference count for a first visited data buffer in the virtual data buffers having an input coupled to a first processing layer in the artificial neural network to a first value equal to a number of processing layers of the artificial neural network having inputs coupled to the first visited data buffer;

initialize a second reference count for a second visited data buffer in the virtual data buffers having an input coupled to a second processing layer in the artificial neural network to a second value equal to the number of processing layers of the artificial neural network having inputs coupled to the second visited data buffer;

decrement the first reference count as a result of visiting one of the processing layers having inputs coupled to the first visited data buffer;

decrement the second reference count as a result of visiting one of the processing layers having inputs coupled to the second visited data buffer;

determine whether the first reference count or the second reference count reached a value of zero as a result of the first reference count and the second reference count being decremented;

deallocate, as a result of a determination that the first reference count or the second reference count reached zero, a visited data buffer whose reference count has reached zero; and

iterate the set of sequential operations until an end of the ordered visiting sequence of layers of the artificial neural network is reached.

15. The system of claim 14 , wherein the processing circuitry is configured to:

initialize a list of memory intervals that includes a set of tuples having values indicative of a base physical memory address and of a maximum heap size; and

sequentially parse the set of instructions included in the virtual memory allocation schedule, wherein

for an instruction parsed in the set of instructions to allocate a first data buffer, allocate the first data buffer to a temporary memory interval having a smallest size sufficient to store the first data buffer;

for an instruction parsed in the set of instructions to deallocate a second data buffer, deallocate the second data buffer from memory; and

merge a memory interval freed as a result of deallocating the second data buffer with one or more free memory intervals in the list of memory intervals; and

update the list of memory intervals based on allocation or deallocation of data buffers specified in the set of instructions, the physical memory configuration dataset is calculated in connection with parsing the set of instructions.

16. A non-transitory computer-readable media storing instructions that, as a result of execution by one or more processors, cause the processors to:

couple virtual data buffers to respective processing layers of an artificial neural network;

obtain an ordered visiting sequence of layers of the artificial neural network;

produce, as a function of the ordered visiting sequence of layers, a virtual memory allocation schedule that includes a set of instructions that specify memory allocation operations and memory deallocation operations applicable to the virtual data buffers; and

compute, based on the virtual memory allocation schedule, a physical memory configuration dataset for the artificial neural network, the physical memory configuration dataset comprising sizes and addresses of physical memory locations of the artificial neural network, wherein

execution of the instructions causes the one or more processors to:

initialize a list of memory intervals that includes a set of tuples having values indicative of a base physical memory address and of a maximum heap size; and

sequentially parse the set of instructions included in the virtual memory allocation schedule; and

execution of the instructions causes the one or more processors to:

allocate, for an instruction parsed in the set of instructions to allocate a first data buffer, the first data buffer to a temporary memory interval having a smallest size sufficient to store the first data buffer;

deallocate, for an instruction parsed in the set of instructions to deallocate a second data buffer, the second data buffer from memory;

merge a memory interval freed as a result of deallocation with one or more free memory intervals in the list of memory intervals; and

update the list of memory intervals based on allocation or deallocation of data buffers specified in the set of instructions, the physical memory configuration dataset in connections calculated in connection with parsing the set of instructions.

17. The non-transitory computer-readable media of claim 16 , execution of the instructions causing the one or more processors to:

configure processing circuitry of the one or more processors according to a directed acyclic graph representing the virtual memory allocation schedule, wherein data buffer nodes in the data buffers in the virtual memory circuitry are coupled to respective layer processing nodes in the processing layers of the artificial neural network.

18. The non-transitory computer-readable media of claim 17 , execution of the instructions causing the one or more processors to:

parse the directed acyclic graph; and

determine dependencies between the processing layers of the artificial neural network.