IP Library › Granted Patent US 11,462,178
Granted Patent B2
US 11,462,178 · App. 17/135,806 · Granted Oct 4, 2022

Display device

Inventors: Jang Mi Kang (Seoul, KR); Ji Sun Kim (Seoul, KR); Mu Kyung Jeon (Ulsan, KR)
Assignee: Samsung Display Co., Ltd.
G09G3/3283G09G3/3233G09G3/3258G09G3/3266G09G3/3291H01L27/124H01L27/1222H01L27/1225H01L27/1251H01L27/1255H01L27/3244G09G2300/043G09G2300/0426G09G2310/0264H01L27/3265H01L27/3276
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Quick Facts
Patent No.
US 11,462,178
App. No.
17/135,806
Granted
Oct 4, 2022
Kind
B2
Abstract

A display device including a light-emitting diode, a first transistor configured to supply a driving current to the light-emitting diode, a second transistor configured to transmit a data signal to the first transistor, a third transistor configured to transmit the data signal compensated with a threshold voltage to a gate electrode of the first transistor, a first scan line connected to a gate electrode of the second transistor, a second scan line connected to a gate electrode of the third transistor and insulated from the first scan line, and a conductive pattern connected to the gate electrode of the first transistor and insulated from the first scan line and the second scan line. The conductive pattern overlaps the first scan line and the second scan line, and the conductive pattern includes a stem part extending in one direction and a branch part branching from the stem part and overlapping the first scan line.

Claims (50)

1. A display device comprising:

a light-emitting diode;

a first transistor configured to supply a driving current to the light-emitting diode;

a second transistor configured to transmit a data signal to the first transistor;

a third transistor configured to transmit the data signal compensated with a threshold voltage to a gate electrode of the first transistor;

a first scan line connected to a gate electrode of the second transistor;

a second scan line connected to a gate electrode of the third transistor and insulated from the first scan line; and

a node portion connected to the gate electrode of the first transistor and a first electrode of the third transistor,

wherein:

the node portion overlaps the first scan line and the second scan line; and

an overlapping area between the node portion and the first scan line is different from an overlapping area between the node portion and the second scan line.

2. The display device of claim 1 , wherein the node portion comprises:

a stem part extending in one direction; and

a branch part branching from the stem part and overlapping the first scan line.

3. The display device of claim 2 , wherein the branch part comprises a first branch part extending in a first direction intersecting a direction to which the stem part extends.

4. The display device of claim 3 , wherein the branch part further comprises a second branch part extending in a second direction opposite to the first direction.

5. The display device of claim 1 , wherein:

the first transistor and the second transistor are PMOS transistors; and

the third transistor is an NMOS transistor.

6. The display device of claim 1 , wherein:

the first transistor and the second transistor comprise polycrystalline silicon; and

the third transistor comprises an oxide semiconductor.

7. The display device of claim 6 , wherein:

a first electrode of the first transistor is connected to a second electrode of the second transistor; and

a second electrode of the first transistor is connected to a second electrode of the third transistor.

8. The display device of claim 1 , further comprising:

a first signal line configured to transmit a first signal having one of a logic high level and a logic low level; and

a second signal line configured to transmit a second signal having the other one of the logic high level and the logic low level at the same point of time.

9. A display device comprising:

a light-emitting diode;

a first transistor configured to supply a driving current to the light-emitting diode;

a second transistor configured to transmit a data signal to the first transistor;

a third transistor configured to transmit the data signal compensated with a threshold voltage to a gate electrode of the first transistor;

a first scan line connected to a gate electrode of the second transistor;

a second scan line connected to a gate electrode of the third transistor and insulated from the first scan line; and

a node portion connected to the gate electrode of the first transistor and a first electrode of the third transistor,

wherein a first capacitance between the node portion and the first scan line is greater than a second capacitance between the node portion and the second scan line.

10. The display device of claim 9 , wherein:

the node portion overlaps the first scan line and the second scan line; and

an overlapping area between the node portion and the first scan line is larger than an overlapping area between the node portion and the second scan line.

11. The display device of claim 9 , wherein the node portion comprises:

a stem part extending in one direction; and

a branch part branching from the stem part and overlapping the first scan line.

12. The display device of claim 11 , wherein the branch part further comprises a second branch part extending in a second direction opposite to the first direction.

13. The display device of claim 9 , wherein:

the first transistor and the second transistor comprise polycrystalline silicon; and

the third transistor comprises an oxide semiconductor.

14. The display device of claim 9 , further comprising:

a first signal line configured to transmit a first signal having one of a logic high level and a logic low level; and

a second signal line configured to transmit a second signal having the other one of the logic high level and the logic low level at the same point of time.

Priority Claims (1)
KR 10-2017-0118887 · Sep 15, 2017 · national
Continuity (2)
Continuation 16129796 · Sep 13, 2018
Related Publication 20210118377A1 · Apr 22, 2021