Lithography process monitoring method
A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.
1. A method of performing a lithography process for a semiconductor device, the method comprising:
providing a test pattern having a plurality of lines;
exposing the test pattern to form a test structure over a semiconductor substrate;
measuring the test structure, wherein the measuring includes:
determining a distance between a first line of the test structure and a second line of the test structure, wherein at least a third line interposes the first line and the second line; and
correlating the distance to an offset of a lithography parameter;
adjusting the lithography parameter based on the measured test structure; and
using the adjusted lithography parameter to expose a circuit pattern on another semiconductor substrate.
2. The method of claim 1 , wherein the determining the distance is performed using a scanning electron microscope.
3. The method of claim 1 , wherein the lithography parameter is one of focus or dose.
4. The method of claim 1 , wherein the plurality of lines includes lines at a first pitch and lines at a second pitch.
5. The method of claim 1 , wherein the measuring the test structure further includes:
determining a first distance between a third line and a first line of the plurality of lines; and
determining a second distance between the third line and a second line of the plurality of lines.
6. The method of claim 5 , further including:
correlating a difference between the second distance and the first distance to another lithography parameter.
7. The method of claim 6 , wherein the another lithography parameter is a best focus.
8. A method of performing a lithography process, the method comprising:
expose a circuit pattern on a first substrate using a first illumination mode of a lithography system;
expose a test pattern on the first substrate using a second illumination mode of the lithography system to form a test structure;
measure a distance between features of the test structure;
correlating the distance to an offset of a lithography parameter; and
adjusting a lithography process of the first illumination mode based on the offset of the lithography parameter.
9. The method of claim 8 , wherein the test pattern includes a plurality of lines.
10. The method of claim 9 , wherein the plurality of lines includes a first line and a second line arranged at a first pitch and a third line arranged at a second pitch from the first line.
11. The method of claim 8 , wherein the first illumination mode and the second illumination mode are extreme ultraviolet (EUV) radiation lithography modes.
12. The method of claim 8 , wherein the first illumination mode and the second illumination mode are immersion lithography process modes.
13. The method of claim 8 , wherein the lithography parameter is one of focus or dose.
14. The method of claim 8 , further comprising: providing the test pattern on a reflective mask.
15. The method of claim 8 , further comprising: providing the test pattern on a transmissive mask.
16. A method, comprising:
performing an exposure process on a first semiconductor substrate using a first illumination mode of a lithography system;
performing a monitoring exposure process on a second semiconductor substrate using a second illumination mode of the lithography system, wherein the monitoring exposure process includes:
irradiating at least a portion of a test pattern providing for a symmetrical diffraction; and
irradiating at least a portion of the test pattern providing for an asymmetrical diffraction;
measuring the test pattern exposed on the second semiconductor substrate to determine a shift of features of the at least the portion of the test pattern; and
using the determined shift to determine a parameter of the lithography system.
17. The method of claim 16 , further comprising:
using the determined parameter of the lithography system when exposing a third semiconductor substrate.
18. The method of claim 17 , wherein the exposing the third semiconductor substrate is performed using the first illumination mode.
19. The method of claim 16 , wherein the first illumination mode is symmetrical irradiation.
20. The method of claim 19 , wherein the second illumination mode is asymmetrical irradiation.