IP Library › Granted Patent US 11,467,648
Granted Patent B2
US 11,467,648 · App. 16/811,663 · Granted Oct 11, 2022

Methods and apparatus to reduce power consumption and improve battery life of display systems using adaptive sync

Inventors: Nausheen Ansari (Folsom, CA); Kevin W. Krueger (El Dorado Hills, CA); Vishal R. Sinha (Portland, OR); Seh Kwa (Saratoga, CA)
Assignee: Intel Corporation
G06F1/3234G06F1/3212G06F8/658
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Quick Facts
Patent No.
US 11,467,648
App. No.
16/811,663
Granted
Oct 11, 2022
Kind
B2
Abstract

Methods, apparatus, systems and articles of manufacture to reduce power consumption and improve battery life of display systems using adaptive sync are disclosed. An example apparatus includes an interface to transmit frame data to a sink device, the frame data generated by a processor; a timer to initiate in response to the transmission of the frame data to the sink device; and the interface to transmit a low power indication to the sink device after the timer reaches a threshold amount of time.

Claims (66)

1. An apparatus comprising:

an interface to transmit frame data to a sink device, the frame data generated by a processor;

a timer to initiate in response to the transmission of the frame data to the sink device;

the interface to transmit a low power indication to the sink device after the timer reaches a threshold amount of time; and

a comparator to compare the frame data to subsequent frame data to determine if the subsequent frame data corresponds to a full update or a partial update, the partial update corresponding to less than a threshold number of pixels updated from the frame data and the subsequent frame data, the timer to (A) reset in response to the full update and (B) not reset in response to the partial update.

2. The apparatus of claim 1 , wherein the interface is a first interface, further including a second interface to obtain the frame data from the processor.

3. The apparatus of claim 2 , wherein the threshold amount of time is a first threshold amount of time, the first interface to, in response to at least one of (A) the timer reaching a second threshold amount of time or (B) the second interface obtaining the subsequent frame data from the processor, transmit a wake up indication to the sink device.

4. The apparatus of claim 3 , wherein the timer is to reset in response to the at least one of (A) the timer reaching the second threshold amount of time or (B) the second interface obtaining the subsequent frame data from the processor.

5. The apparatus of claim 2 , wherein:

the second interface is to obtain the subsequent frame data from the processor; and

the first interface is to:

transmit a wake up indication to the sink device; and

transmit the subsequent frame data to the sink device after the wake up indication.

6. The apparatus of claim 2 , wherein the second interface is to obtain the subsequent frame data from the processor.

7. The apparatus of claim 1 , wherein the threshold amount of time is a first threshold amount of time, the interface to:

transmit a wake up indication to the sink device in response to the timer reaching a second threshold amount of time; and

in response to transmitting the wake up indication, retransmit the frame data to the sink device.

8. The apparatus of claim 1 , wherein the low power indication causes the sink device to turn off a component.

9. A non-transitory computer readable medium comprising instructions which, when executed, cause one or more processors to at least:

transmit frame data to a sink device, the frame data generated by a processor;

initiate a timer in response to the transmission of the frame data to the sink device;

transmit a low power indication to the sink device after the timer reaches a threshold amount of time;

compare the frame data to first subsequent frame data to determine that the first subsequent frame data corresponds to a full update;

compare the frame data to second subsequent frame data to determine that the second subsequent frame data corresponds to a partial update, the partial update corresponding to less than a threshold number of pixels updated from the frame data and the second subsequent frame data; and

reset the timer in response to the full update and not reset the timer in response to the partial update.

10. The computer readable medium of claim 9 , wherein the instructions cause the one or more processors to obtain the frame data from the processor.

11. The computer readable medium of claim 10 , wherein the threshold amount of time is a first threshold amount of time, the instructions to cause the one or more processors to, in response to at least one of (A) the timer reaching a second threshold amount of time or (B) obtaining the first subsequent frame data from the processor, transmit a wake up indication to the sink device.

12. The computer readable medium of claim 11 , wherein the instructions cause the one or more processors to reset the timer in response to the at least one of (A) the timer reaching the second threshold amount of time or (B) obtaining the first subsequent frame data from the processor.

13. The computer readable medium of claim 10 , wherein the instructions cause the one or more processors to:

obtain the first subsequent frame data from the processor;

transmit a wake up indication to the sink device; and

transmit the first subsequent frame data to the sink device after the wake up indication.

14. The computer readable medium of claim 10 , wherein the instructions cause the one or more processors to obtain the first subsequent frame data from the processor.

15. The computer readable medium of claim 9 , wherein the threshold amount of time is a first threshold amount of time, the instructions to cause the one or more processors to:

transmit a wake up indication to the sink device in response to the timer reaching a second threshold amount of time; and

in response to transmitting the wake up indication, retransmit the frame data to the sink device.

16. The computer readable medium of claim 9 , wherein the low power indication causes the sink device to turn off a component.

17. A method comprising:

transmitting frame data to a sink device, the frame data generated by a processor;

initiating, by executing an instruction with one or more processors, a timer in response to the transmission of the frame data to the sink device;

transmitting a low power indication to the sink device after the timer reaches a threshold amount of time;

comparing the frame data to subsequent frame data to determine if the subsequent frame data corresponds to a full update or a partial update, the partial update corresponding to less than a threshold number of pixels updated from the frame data and the subsequent frame data;

in response to determining that the subsequent frame data corresponds to a full update, resetting the timer in response to the full update; and

in response to determining that the subsequent frame data corresponds to a partial update, continuing the timer.

18. The method of claim 17 , further including obtaining the frame data from the processor.

19. An apparatus comprising:

memory;

instructions in the apparatus; and

processor circuitry to execute the instruction to:

transmit frame data to a sink device, the frame data generated by a processor;

initiate a timer in response to the transmission of the frame data to the sink device;

transmit a low power indication to the sink device after the timer reaches a threshold amount of time;

compare the frame data to subsequent frame data to determine if the subsequent frame data corresponds to a full update or a partial update, the partial update corresponding to less than a threshold number of pixels updated from the frame data and the subsequent frame data;

reset the timer based on the subsequent frame data corresponding to the full update; and

maintain the timer based on the subsequent frame data corresponding to the partial update.

20. The apparatus of claim 19 , wherein the processor circuitry is to obtain the frame data from the processor.

21. The apparatus of claim 20 , wherein the threshold amount of time is a first threshold amount of time, the processor circuitry to, in response to at least one of (A) the timer reaching a second threshold amount of time or (B) obtaining the subsequent frame data from the processor, transmit a wake up indication to the sink device.

22. The apparatus of claim 21 , wherein the processor circuitry is to reset the timer in response to the at least one of (A) the timer reaching the second threshold amount of time or (B) obtaining the subsequent frame data from the processor.

23. The apparatus of claim 20 , wherein the processor circuitry is to:

obtain the subsequent frame data from the processor;

transmit a wake up indication to the sink device; and

transmit the subsequent frame data to the sink device after the wake up indication.

24. The apparatus of claim 19 , wherein the threshold amount of time is a first threshold amount of time, the processor circuitry to:

transmit a wake up indication to the sink device in response to the timer reaching a second threshold amount of time; and

in response to transmitting the wake up indication, retransmit the frame data to the sink device.

25. The apparatus of claim 19 , wherein the low power indication causes the sink device to turn off a component.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2020
From: ANSARI, NAUSHEEN; KRUEGER, KEVIN W.; SINHA, VISHAL R.; KWA, SEH
To: INTEL CORPORATION
Reel/Frame 052296/0104 →
Continuity (1)
Related Publication 20200278735A1 · Sep 3, 2020