IP Library › Granted Patent US 11,467,938
Granted Patent B2
US 11,467,938 · App. 17/026,544 · Granted Oct 11, 2022

Read retry threshold optimization systems and methods conditioned on previous reads

Inventors: Meysam Asadi (Fremont, CA); Aman Bhatia (Los Gatos, CA); Fan Zhang (Fremont, CA)
Assignee: SK hynix Inc.
G06F11/3037G06F11/076G06K9/6215G11C16/14G11C16/26G11C16/3431
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,467,938
App. No.
17/026,544
Granted
Oct 11, 2022
Kind
B2
Abstract

A controller optimizes read retry thresholds for a memory device using one or more previous reads and a condition. The controller determines a read level table based on a condition indicative of a state of the memory device and selects an entry among multiple entries in the selected read level table based on a historical read threshold. For the selected entry, the controller: determines fail bits for data associated with multiple read operations on the cells using multiple read retry thresholds; and determines an order of the multiple read retry thresholds based on the fail bits determination.

Claims (68)

1. A memory system comprising:

a memory device including a plurality of cells; and

a controller coupled to the memory device and configured to:

select from plural read level tables a read level table based on an operational condition indicative of a present state of the memory device at a time of reading the cells, the read level table including multiple entries, each entry including a set of read thresholds including a historical read threshold and multiple read retry thresholds;

select an entry among the multiple entries in the selected read level table based on the historical read threshold;

for the selected entry,

determine fail bits for data associated with multiple read operations on the plurality of cells using the multiple read retry thresholds; and

arrange an order of the multiple read retry thresholds based on the fail bits determination.

2. The memory system of claim 1 , wherein the condition includes combinations of values from an erase/write (EW) cycle array of values, a single page read (SPRD) cycle array of values and type of page associated with the plurality of cells.

3. The memory system of claim 1 , wherein the controller is configured to:

determine the order of the multiple read retry thresholds to be an ascending order of fail bit counts.

4. The memory system of claim 1 , wherein the controller is further configured to:

estimate two conditions closest to the condition when the condition does not correspond to any of multiple defined conditions;

select from the plural read level tables two read level tables corresponding to the two conditions; and

use the two read threshold tables to perform selecting an entry, determining fail bits and determining the order of the multiple read thresholds.

5. The memory system of claim 4 , wherein the controller is configured to:

perform interpolation with respect to the two read level tables to generate an interpolated read level table and use the interpolated read level table to perform selecting an entry, determining fail bits and determining the order of the multiple read thresholds.

6. The memory system of claim 1 , wherein the controller is further configured to:

when the historical read threshold is not included in a set of default read thresholds, which correspond to multiple historical read thresholds in the multiple entries, compute a set distance between the historical read threshold and each of the multiple read thresholds; and

select a historical read threshold with the lowest distance, among the set of the default read thresholds.

7. The memory system of claim 6 , wherein the controller is further configured to:

for an entry with the selected read threshold as a historical read threshold,

determine fail bits and determine the order of the multiple read thresholds.

8. The memory system of claim 6 , wherein the set distance includes an Euclidean distance.

9. A method for operating a memory system including a memory device including a plurality of cells and a controller, the method comprising:

selecting from plural read level tables a read level table based on an operational condition indicative of a present state of the memory device at a time of reading the cells, the read level table including multiple entries, each entry including a set of read thresholds including a historical read threshold and multiple read retry thresholds;

selecting an entry among the multiple entries in the selected read level table based on the historical read threshold;

for the selected entry,

determining fail bits for data associated with multiple read operations on the plurality of cells using the multiple read retry thresholds; and

arranging an order of the multiple read retry thresholds based on the fail bits determination.

10. The method of claim 9 , wherein the condition includes combinations of values from an erase/write (EW) cycle array of values, a single page read (SPRD) cycle array of values and a type of a page associated with the plurality of cells.

11. The method of claim 9 , wherein the determining of the order of the multiple read retry thresholds includes:

determining the order of the multiple read retry thresholds to be an ascending order of fail bit counts.

12. The method of claim 9 , further comprising:

estimating two conditions closest to the condition when the condition does not correspond to any of multiple defined conditions;

selecting from the plural read level tables two read level tables corresponding to the two conditions; and

using the two read threshold tables to perform selecting an entry, determining fail bits and determining the order of the multiple read thresholds.

13. The method of claim 12 , further comprising:

performing interpolation with respect to the two read level tables to generate an interpolated read level table and using the interpolated read level table to perform selecting an entry, determining fail bits and determining the order of the multiple read thresholds.

14. The method of claim 9 , further comprising:

when the historical read threshold is not included in a set of default read thresholds, which correspond to multiple historical read thresholds in the multiple entries, computing a set distance between the historical read threshold and each of the multiple read thresholds; and

selecting a historical threshold with the lowest distance, among the set of the default read thresholds.

15. The method of claim 14 , further comprising:

for an entry with the selected read threshold as a historical read threshold,

determining counting fail bits and determining the order of the multiple read thresholds.

16. The method of claim 14 , wherein the set distance includes an Euclidean distance.

17. A memory system comprising:

a memory device including a plurality of cells; and

a controller coupled to the memory device and configured to:

select from plural read level tables a read level table based on an operational condition indicative of a present state of the memory device at a time of reading the cells, the read level table including multiple entries, each entry including a set of read thresholds including a historical read threshold and multiple read retry thresholds;

determine whether the historical read threshold is included in a set of default read thresholds, which correspond to multiple historical read thresholds in the multiple entries;

determine whether the condition corresponds to any of multiple defined conditions;

when it is determined that the historical read threshold is included in the set of the default read thresholds and the condition corresponds to any of the multiple defined conditions, select an entry among the multiple entries in the selected read level table based on the historical read threshold;

for the selected entry,

determine fail bits for data associated with multiple read operations on the plurality of pages using the multiple read retry thresholds; and

arrange an order of the multiple read retry thresholds based on the fail bits determination.

18. The memory system of claim 17 , wherein the condition include combinations of values from an erase/write (EW) cycle array of values, a single page read (SPRD) cycle array of values and type of page associated with the plurality of cells, and

wherein the controller is configured to:

determine the order of the multiple read retry thresholds to be an ascending order of fail bit counts.

19. The memory system of claim 17 , wherein the controller is further configured to:

estimate two conditions closest to the condition when the condition does not correspond to any of multiple defined conditions;

select from the plural read level tables two read level tables corresponding to the two conditions; and

perform interpolation with respect to the two read level tables to generate an interpolated read level table and use the interpolated read bias table to perform selecting an entry, determining fail bits and determining the order of the multiple read thresholds.

20. The memory system of claim 17 , wherein the controller is further configured to:

when it is determined that the historical read threshold is not included in the set of the default read thresholds, compute a set distance between the historical read threshold and each of the multiple read thresholds;

select a historical read threshold with the lowest distance, among the set of the default read thresholds; and

for an entry with the selected read threshold as a historical read threshold,

determine fail bits and determine the order of the multiple read thresholds.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2022
From: SK HYNIX MEMORY SOLUTIONS AMERICA INC.
To: SK HYNIX INC.
Reel/Frame 061209/0467 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2020
From: ASADI, MEYSAM; BHATIA, AMAN; ZHANG, FAN
To: SK HYNIX MEMORY SOLUTIONS AMERICA INC.
Reel/Frame 053828/0629 →
Continuity (1)
Related Publication 20220091953A1 · Mar 24, 2022
Cited By (1)
US 12,451,198