Virtualization-based platform protection technology
A data processing system (DPS) uses platform protection technology (PPT) to protect some or all of the code and data belonging to certain software modules. The PPT may include a virtual machine monitor (VMM) to enable an untrusted application and a trusted application to run on top of a single operating system (OS), while preventing the untrusted application from accessing memory used by the trusted application. The VMM may use a first extended page table (EPT) to translate a guest physical address (GPA) into a first host physical address (HPA) for the untrusted application. The VMM may use a second EPT to translate the GPA into a second HPA for the trusted application. The first and second EPTs may map the same GPA to different HPAs. Other embodiments are described and claimed.
1. A method comprising:
enabling, by a data processing system, an untrusted application and a trusted application to run on top of a single operating system (OS), while preventing the untrusted application from accessing memory used by the trusted application, wherein the OS comprises an untrusted interrupt descriptor table (IDT) with gates that associate interrupt vectors with untrusted interrupt service routines (ISRs);
creating, by the data processing system, a virtual IDT (VIDT) with gates that associate interrupt vectors with trusted ISRs, wherein the trusted ISRs comprise a trusted application (TA)-enter ISR that causes the data processing system to switch from an untrusted memory view associated with the untrusted application to a trusted memory view associated with the trusted application;
configuring, by the data processing system, a processor of the data processing system to use the VIDT instead of the untrusted IDT (UIDT); and
responding, by the data processing system and after configuring the processor, to a TA-enter interrupt by invoking the TA-enter ISR.
2. The method of claim 1 , further comprising:
storing, by a virtual machine monitor (VMM) of the data processing system, the trusted ISRs in a trusted kernel context (TKC); and
preventing, by the VMM, the OS from modifying the TKC.
3. The method of claim 1 , wherein the trusted ISRs further comprise a TA-exit ISR, and further comprising:
switching, by the TA-exit ISR and in response to a TA-exit interrupt, from the trusted memory view associated with the trusted application to the untrusted memory view associated with the untrusted application.
4. The method of claim 1 , wherein the trusted ISRs further comprise a TA-resume ISR, and further comprising:
in response to a TA-resume interrupt, (i) switching, by the TA-resume ISR, from the untrusted memory view associated with the untrusted application to the trusted memory view associated with the untrusted application and (ii) restoring, by the TA-resume ISR, context for the trusted application.
5. The method of claim 1 , wherein the trusted ISRs further comprise a general purpose (GP) ISR, and further comprising:
determining, by the GP ISR and in response to an interrupt, whether the interrupt occurred while the trusted application is executing; and
in response to determining that the interrupt occurred while the trusted application is executing:
saving, by the GP ISR, state data from at least one register to a save state area (SSA) for the trusted application; and
replacing, by the GP ISR, a return instruction pointer (RIP) on a current trusted stack with an asynchronous exit pointer (AEP) of an untrusted runtime associated with the untrusted application.
6. A data processing system comprising:
one or more processors; and
one or more memory devices having stored therein a plurality of instructions that, when executed by the one or more processors, causes the data processing system to:
enable an untrusted application and a trusted application to run on top of a single operating system (OS), while preventing the untrusted application from accessing memory used by the trusted application, wherein the OS comprises an untrusted interrupt descriptor table (IDT) with gates that associate interrupt vectors with untrusted interrupt service routines (ISRs);
create a virtual IDT (VIDT) with gates that associate interrupt vectors with trusted ISRs, wherein the trusted ISRs comprise a trusted application (TA)-enter ISR that causes the data processing system to switch from an untrusted memory view associated with the untrusted application to a trusted memory view associated with the trusted application;
configure a processor of the one or more processors to use the VIDT instead of the untrusted IDT (UIDT); and
respond, after configuring the processor, to a TA-enter interrupt by invoking the TA-enter ISR.
7. The data processing system of claim 6 , wherein the plurality of instructions, when executed, further cause the data processing system to:
store, by a virtual machine monitor (VMM) of the data processing system, the trusted ISRs in a trusted kernel context (TKC); and
prevent, by the VMM, the OS from modifying the TKC.
8. The data processing system of claim 6 , wherein the trusted ISRs further comprise a TA-exit ISR, and wherein the plurality of instructions, when executed, further cause the data processing system to:
switch, by the TA-exit ISR and in response to a TA-exit interrupt, from the trusted memory view associated with the trusted application to the untrusted memory view associated with the untrusted application.
9. The data processing system of claim 6 , wherein the trusted ISRs further comprise a TA-resume ISR, and wherein the plurality of instructions, when executed, further cause the data processing system to:
in response to a TA-resume interrupt, (i) switch, by the TA-resume ISR, from the untrusted memory view associated with the untrusted application to the trusted memory view associated with the untrusted application and (ii) restore, by the TA-resume ISR, context for the trusted application.
10. The data processing system of claim 6 , wherein the trusted ISRs further comprise a general purpose (GP) ISR, and wherein the plurality of instructions, when executed, further cause the data processing system to:
determine, by the GP ISR and in response to an interrupt, whether the interrupt occurred while the trusted application is executing; and
in response to determination that the interrupt occurred while the trusted application is executing:
save, by the GP ISR, state data from at least one register to a save state area (SSA) for the trusted application; and
replace, by the GP ISR, a return instruction pointer (RIP) on a current trusted stack with an asynchronous exit pointer (AEP) of an untrusted runtime associated with the untrusted application.
11. An apparatus comprising:
one or more processors coupled to memory, the one or more processors to:
enable an untrusted application and a trusted application to run on top of a single operating system (OS), while preventing the untrusted application from accessing memory used by the trusted application, wherein the OS comprises an untrusted interrupt descriptor table (IDT) with gates that associate interrupt vectors with untrusted interrupt service routines (ISRs);
create a virtual IDT (VIDT) with gates that associate interrupt vectors with trusted ISRs, wherein the trusted ISRs comprise a trusted application (TA)-enter ISR that causes the data processing system to switch from an untrusted memory view associated with the untrusted application to a trusted memory view associated with the trusted application;
configure a processor of the one or more processors to use the VIDT instead of the untrusted IDT (UIDT); and
respond, after configuring the processor, to a TA-enter interrupt by invoking the TA-enter ISR.
12. The apparatus of claim 11 , wherein the plurality of instructions, when executed, further cause the data processing system to:
store, by a virtual machine monitor (VMM), the trusted ISRs in a trusted kernel context (TKC); and
prevent, by the VMM, the OS from modifying the TKC.
13. The apparatus of claim 11 , wherein the trusted ISRs further comprise a TA-exit ISR, and wherein the one or more processors are further to:
switch, by the TA-exit ISR and in response to a TA-exit interrupt, from the trusted memory view associated with the trusted application to the untrusted memory view associated with the untrusted application.
14. The apparatus of claim 11 , wherein the trusted ISRs further comprise a TA-resume ISR, and wherein the one or more processors are further to:
in response to a TA-resume interrupt, (i) switch, by the TA-resume ISR, from the untrusted memory view associated with the untrusted application to the trusted memory view associated with the untrusted application and (ii) restore, by the TA-resume ISR, context for the trusted application.
15. The apparatus of claim 11 , wherein the trusted ISRs further comprise a general purpose (GP) ISR, and wherein the one or more processors are further to:
determine, by the GP ISR and in response to an interrupt, whether the interrupt occurred while the trusted application is executing; and
in response to determination that the interrupt occurred while the trusted application is executing:
save, by the GP ISR, state data from at least one register to a save state area (SSA) for the trusted application; and
replace, by the GP ISR, a return instruction pointer (RIP) on a current trusted stack with an asynchronous exit pointer (AEP) of an untrusted runtime associated with the untrusted application.