Memory architecture with pulsed-bias power
Various implementations described herein are related to a device having memory circuitry with an array of bitcells coupled to a power rail. The device may have pulse-bias circuitry with stacks of transistors that are coupled to the power rail. In various instances, the stacks of transistors may be alternately activated so as to thereby provide a pulse-biased power supply to the array of bitcells via the power rail.
1. A device comprising:
memory circuitry having an array of bitcells coupled to a power rail; and
pulse-bias circuitry having stacks of transistors coupled to the power rail, wherein the stacks of transistors are alternately activated to provide a pulse-biased power supply to the array of bitcells via the power rail,
wherein the pulse-bias circuitry has programmable delay logic that provides a pulsed-bias input to gates of the stacks of transistors so as to assist the stacks of transistors with generating the pulse-biased power supply with a reduced pulse width.
2. The device of claim 1 , wherein:
the stacks of transistors are alternately activated and deactivated using bias-enable inputs along with the pulsed-bias inputs to generate the pulse-biased power supply.
3. The device of claim 2 , wherein:
the stacks of transistors include a first pull-up stack of transistors and a second pull-up stack of transistors that are coupled in parallel to the power rail,
the bias-enable inputs include a first bias-enable input that is applied to gates of the first pull-up stack of transistors, and
the bias-enable inputs include a second bias-enable input that is applied to gates of the second pull-up stack of transistors.
4. The device of claim 3 , wherein:
the first pull-up stack of transistors includes a first pair of transistors coupled in series between a source power supply and the power rail,
the first bias-enable input is applied to a gate of an upper transistor of the first pair of transistors for activation and deactivation of the upper transistor, and
the pulsed-bias input is applied to a gate of a lower transistor of the first pair of transistors for activation and deactivation of the lower transistor.
5. The device of claim 3 , wherein:
the second pull-up stack of transistors includes a second pair of transistors coupled in series between a source power supply and the power rail,
the second bias-enable input is applied to a gate of an upper transistor of the second pair of transistors for activation and deactivation of the upper transistor, and
the pulsed-bias input is applied to a gate of a lower transistor of the second pair of transistors for activation and deactivation of the lower transistor.
6. The device of claim 1 , wherein:
the programmable delay logic is implemented as a programmable delayed buffer or a programmable metal load, and
the pulsed-bias input is enabled after pulling-down the power rail to a lower level based on the programmable delayed buffer or the programmable metal load.
7. The device of claim 6 , wherein:
a voltage level on the power rail is stabilized after activating the stacks of transistors with the programmable delayed buffer or the programmable metal load, and
direct-current (DC) power consumption is reduced during fall of the voltage level along with improvement of fall-time of the voltage level.
8. The device of claim 7 , further comprising:
precharge circuitry having a transistor coupled to the power rail, wherein the transistor precharges the power rail to a source power supply when activated; and
reset-assist logic coupled to the power rail, wherein the read-assist logic assists the transistor with pre-charging the power rail.
9. The device of claim 8 , wherein:
the pulse-bias circuitry provides the pulse-biased power supply to the power rail during a pulse-biasing cycle, and
the precharge circuitry is configured to precharge the power rail at an end of the pulse-biasing cycle based on a reset-assist signal.
10. A memory device comprising:
an array of bitcells coupled to a voltage rail;
stacks of transistors that are alternately activated to generate a pulse-biased voltage supply to the array of bitcells via the voltage rail; and
programmable delay logic that provides a pulsed-bias input to alternately enable the stacks of transistors so as thereby assist the stacks of transistors with generating the pulse-biased voltage supply with a reduced pulse width.
11. The memory device of claim 10 , wherein:
the stacks of transistors are alternately activated and deactivated using bias-enable inputs along with the pulsed-bias inputs to generate the pulse-biased power supply.
12. The memory device of claim 11 , wherein:
the stacks of transistors include a first pull-up stack of transistors and a second pull-up stack of transistors that are coupled in parallel to the voltage rail,
the bias-enable inputs include a first bias-enable input that is applied to gates of the first pull-up stack of transistors, and
the bias-enable inputs include a second bias-enable input that is applied to gates of the second pull-up stack of transistors.
13. The memory device of claim 12 , wherein:
the first pull-up stack of transistors includes a first pair of transistors coupled in series between a source power supply and the voltage rail,
the first bias-enable input is applied to a gate of an upper transistor of the first pair of transistors for activation and deactivation of the upper transistor, and
the pulsed-bias input is applied to a gate of a lower transistor of the first pair of transistors for activation and deactivation of the lower transistor.
14. The memory device of claim 12 , wherein:
the second pull-up stack of transistors includes a second pair of transistors coupled in series between a source power supply and the voltage rail,
the second bias-enable input is applied to a gate of an upper transistor of the second pair of transistors for activation and deactivation of the upper transistor, and
the pulsed-bias input is applied to a gate of a lower transistor of the second pair of transistors for activation and deactivation of the lower transistor.
15. The memory device of claim 10 , wherein:
the programmable delay logic is implemented as a programmable delayed buffer or a programmable metal load, and
the pulsed-bias input is enabled after pulling-down the voltage rail to a lower level based on the programmable delayed buffer or the programmable metal load.
16. The memory device of claim 15 , wherein:
a voltage level on the voltage rail is stabilized after activating the stacks of transistors with the programmable delayed buffer or the programmable metal load, and
direct-current (DC) power consumption is reduced during fall of the voltage level along with improvement of fall-time of the voltage level.
17. The memory device of claim 16 , further comprising:
precharge logic having a transistor coupled to the voltage rail, wherein the transistor precharges the voltage rail to a source power supply when activated; and
reset-assist logic coupled to the voltage rail, wherein the read-assist logic assists the transistor with pre-charging the voltage rail.
18. The memory device of claim 17 , wherein:
the programmable delay logic provides the pulse-biased power supply to the voltage rail during a pulse-biasing cycle, and
the precharge logic is configured to precharge the voltage rail at an end of the pulse-biasing cycle based on a reset-assist signal.
19. A method comprising:
fabricating memory circuitry with an array of bitcells coupled to a power rail;
fabricating pulse-bias circuitry with stacks of transistors that are alternately activated to provide a pulse-biased power supply to the array of bitcells via the power rail; and
fabricating programmable delay logic that provides a pulsed-bias input to alternately activate the stacks of transistors so as assist with generating the pulse-biased power supply with a reduced pulse width.