IP Library › Granted Patent US 11,468,951
Granted Patent B2
US 11,468,951 · App. 17/458,186 · Granted Oct 11, 2022

Method for programming flash memory

Inventors: Hong Nie (Shanghai, CN); Jingwei Chen (Shanghai, CN)
Assignee: CHINA FLASH CO., LTD.
G11C16/10G11C16/0408G11C16/14H01L27/11521H01L29/7881G11C16/0425
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Quick Facts
Patent No.
US 11,468,951
App. No.
17/458,186
Granted
Oct 11, 2022
Kind
B2
Abstract

The present disclosure relates to a method for programming flash memory, which includes: providing a flash memory structure having a floating gate, and floating a source of the flash memory structure; separately applying voltages to a drain and a substrate, to form an electric field, and generating electron-hole pairs, to generate primary electrons, where the voltage applied to the substrate is less than the voltage applied to the drain; accelerating holes downward under the action of the electric field to collide with the substrate in the flash memory structure within a preset time, to generate secondary electrons; and separately applying voltages to a gate and the substrate, where the voltage applied to the substrate is less than the voltage applied to the gate, and enabling the secondary electrons to generate tertiary electrons to inject the tertiary electrons into the floating gate, to complete a programming operation.

Claims (19)

1. A method for programming flash memory, at least comprising:

a first step: providing a flash memory structure with a floating gate, and floating a source of the flash memory structure;

a second step: after the first step, separately applying voltages to a drain and a substrate of the flash memory structure, to form a lateral electric field, generate electron-hole pairs, and generate primary electrons, wherein the voltage applied to the substrate is less than the voltage applied to the drain;

a third step: after the second step, accelerating holes downward under the action of the lateral electric field to collide with the substrate in the flash memory structure within a preset time, to generate secondary electrons; and

a fourth step: after the third step, separately applying second voltages to a gate and the substrate of the flash memory structure, to form a vertical electric field, wherein the voltage applied to the substrate is less than the voltage applied to the gate, and enabling the secondary electrons to generate tertiary electrons under the action of the vertical electric field, wherein the vertical electric field then injects the tertiary electrons into the floating gate of the flash memory structure, to complete a programming operation of the flash memory structure.

2. The method for programming flash memory as in claim 1 , wherein

the flash memory structure comprises an electrically erasable programmable read-only memory (EEPROM) with tunnel oxide (ETOX) structure, a 1.5 T structure, a 2 T structure, or an EEPROM structure.

3. The method for programming flash memory as in claim 1 , wherein

a difference between the voltage applied to the drain and the voltage applied to the substrate in the second step is not less than 4 V.

4. The method for programming flash memory as in claim 1 , wherein

the preset time in the third step is from 10 ns to 100 ns.

5. The method for programming flash memory as in claim 1 , wherein

a difference between the voltage applied to the gate and the voltage applied to the substrate in the fourth step is not less than 7 V.

6. The method for programming flash memory as in claim 1 , before the first step, further comprising:

pre-erasing the flash memory structure to eliminate residual charges in the floating gate.

7. The method for programming flash memory as in claim 6 , wherein the pre-erasing comprises:

separately applying voltages to the gate and the substrate of the flash memory structure, wherein the voltage applied to the substrate is higher than the voltage applied to the gate.

8. The method for programming flash memory as in claim 7 , wherein

a difference between the voltage applied to the gate and the voltage applied to the substrate is not less than 10 V.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2021
From: NIE, HONG; CHEN, JINGWEI
To: CHINA FLASH CO., LTD.
Reel/Frame 057304/0325 →
Priority Claims (1)
CN 202010954474.5 · Sep 11, 2020 · national
Continuity (1)
Related Publication 20220084599A1 · Mar 17, 2022