Memory controller, memory device and storage device
A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.
1. A memory controller, comprising:
an interface for communicating with a memory device which includes a first die and a second die, the first die including a first block and a second block, and the second die including a third block and a fourth block; and
a control module which manages the memory device in units of a first super block and a second super block, the first super block including the first block and the third block, and the second super block including the second block and the fourth block,
wherein the control module completes a program on the first super block and an erase on the second super block before starting the program on the second super block, and performs the erase on the second super block divided into multiple steps,
completion of the program on the first super block and the erase on the second super block includes
performing a first step erase of the second block, after programming a first portion of the first block,
programming a second portion of the first block, after the first step erase of the second block, and
performing a second step erase of the second block, after programming the second portion of the first block.
2. The memory controller of claim 1 , wherein completion of the program on the first super block and the erase on the second super block includes
performing a first step erase of the fourth block, after programming a third portion of the third block,
programming a fourth portion of the third block, after the first step erase of the fourth block, and
performing a second step erase of the fourth block, after programming the fourth portion of the third block.
3. The memory controller of claim 2 , wherein a first step erase section of the second block and a first step erase section of the fourth block only partially overlap or do not overlap each other.
4. The memory controller of claim 1 , further comprising:
a first queue which stores program commands for the first die, and a second queue which stores erase commands for the first die and is different from the first queue.
5. The memory controller of claim 4 , further comprising:
a third queue which stores program commands for the second die, and a fourth queue which stores erase command for the second die and is different from the third queue.
6. The memory controller of claim 1 , wherein performing of the first step erase of the second block includes
performing the first step erase of the second block, when a current throughput of the first die is greater than a threshold throughput after programming the first portion of the first block.
7. The memory controller of claim 6 , wherein programming of the second portion of the first block includes
programming the second portion of the first block, when the current throughput of the first die becomes equal to or smaller than the threshold throughput during the first step erase.
8. The memory controller of claim 1 , wherein when the program of the first block is performed, a current throughput of the first die increases, and when the erase of the second block is performed, the current throughput of the first die decreases, and
completion of the program on the first super block and the erase on the second super block includes
alternately performing the program on the first block and the erase on the second block to control so that the current throughput of the first die is located between a threshold throughput and a maximum throughput.
9. The memory controller of claim 1 , wherein a first duration of the first step erase is shorter than a second duration of the second step erase.
10. The memory controller of claim 9 , further comprising:
programming a third portion of the first block after the second step erase of the second block; and
performing a third step erase of the second block after programming the third portion of the first block,
wherein the second duration of the second step erase is longer than a third duration of the third step erase.
11. The memory controller of claim 9 , wherein when the program on the first block is performed, a current throughput of the first die increases, and when the erase on the second block is performed, the current throughput of the first die decreases,
the control module sets a first maximum throughput corresponding to the first portion of the first block and a second maximum throughput corresponding to the second portion of the first block so that the second maximum throughput is higher than the first maximum throughput,
when the first portion of the first block is programmed, the current throughput of the first die becomes the first maximum throughput, and when the second block starts the first step erase, the current throughput of the first die decreases from the first maximum throughput, and
when the second portion of the first block is programmed, the current throughput of the first die becomes the second maximum throughput, and when the second block starts the second step erase, the current throughput of the first die decreases from the second maximum throughput.
12. The memory controller of claim 1 , wherein a maximum throughput of the memory device is larger than a host interface max write throughput.
13. A memory device, comprising:
a first die including a first block and a second block; and
a second die including a third block and a fourth block,
wherein the memory device is controlled in units of a first super block and a second super block, the first super block including the first block and the third block, and the second super block including the second block and the fourth block,
before starting a program on the second super block, a program on the first super block and an erase on the second super block are completed, and the erase on the second super block is performed divided into multiple steps,
completion of the program on the first super block and the erase on the second super block includes
performing a first step erase of a second block, after programming a first portion of the first block,
programming a second portion of the first block, after the first step erase of the second block, and
performing a second step erase of the second block, after programming the second portion of the first block.
14. The memory device of claim 13 , wherein a first duration of the first step erase is shorter than a second duration of the second step erase.
15. A storage device, comprising:
a memory device which includes a first die and a second die, the first die including a first block and a second block, and the second die including a third block and a fourth block; and
a controller which manages the memory device by a first super block or a second super block, the first super block including the first block and the third block, and the second super block including the second block and he fourth block,
wherein the controller completes a program on the first super block and an erase on the second super block before starting the program on the second super block, and performs the erase on the second super block divided into multiple steps, and
the program on the first super block and the erase on the second super block include
performing a first step erase of a second block, after programming a first portion of the first block,
programming a second portion of the first block, after the first step erase of the second block, and
performing a second step erase of the second block, after programming the second portion of the first block.
16. The storage device of claim 15 , wherein the program on the first super block and the erase on the second super block include
performing the first step erase of the fourth block, after programming a third portion of the third block,
programming a fourth portion of the third block, after the first step erase of the fourth block, and
performing the second step erase of the fourth block, after programming the fourth portion of the third block, and
a first step erase section of the second block and a first step erase section of the fourth block only partially overlap or do not overlap each other.
17. The storage device of claim 15 , wherein the controller further comprises:
a first queue which stores a program command for the first die, and a second queue which stores an erase command for the first die and is different from the first queue,
wherein the controller checks the program command and the erase command and performs a scheduling operation.
18. The storage device of claim 15 , wherein the first step erase of the second block includes the first step erase of the second block, when a current throughput of the first die is greater than a threshold throughput after programming the first portion of the first block, and
programming the second portion of the first block includes programming the second portion of the first block, when the current throughput of the first die becomes equal to or smaller than the threshold throughput, during the first step erase.
19. The storage device of claim 15 , wherein the controller further comprises:
programming a third portion of the first block, after the second step erase of the second block, and
performing a third step erase of the second block, after programming the third portion of the first block, and
a second duration of the second step erase is longer than a first duration of the first step erase and a third duration of the third step erase.
20. The storage device of claim 15 , wherein when the program on the first block is performed, a current throughput of the first die increases, and when the erase on the second block is performed, the current throughput of the first die decreases,
a control module sets a first maximum throughput corresponding to the first portion of the first block, and a second maximum throughput corresponding to the second portion of the first block so that the second maximum throughput is higher than the first maximum throughput,
when the first portion of the first block is programmed, the current throughput of the first die becomes the first maximum throughput, and when the second block starts the first step erase, the current throughput of the first die decreases from the first maximum throughput, and
when the second portion of the first block is programmed, the current throughput of the first die becomes the second maximum throughput, and when the second block starts the second step erase, the current throughput of the first die decreases from the second maximum throughput.