Ferroelectric gate stack for band-to-band tunneling reduction
Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.
1. An integrated circuit comprising:
a gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode, wherein the interfacial oxide layer is between the ferroelectric layer and the gate electrode, and wherein the ferroelectric layer includes ferroelectric material;
first and second gate spacers adjacent to respective sides of the gate stack;
a base layer below the gate stack and comprising a semiconductor material, wherein the ferroelectric layer is between the base layer and the interfacial oxide layer, and wherein the ferroelectric layer is on and in direct contact with the base layer; and
a source region and a drain region to both sides of the gate stack.
2. The integrated circuit of claim 1 , wherein the base layer includes group III-V semiconductor material.
3. The integrated circuit of claim 1 , wherein the base layer includes gallium and nitrogen.
4. The integrated circuit of claim 1 , wherein the source and drain regions both include indium and nitrogen.
5. The integrated circuit of claim 1 , wherein material of the source and drain regions is n-type doped.
6. The integrated circuit of claim 1 , wherein the ferroelectric material includes at least one of BaTiO 3 , PbTiO 3 , KNbO 3 , LiTaO 3 , BiFeO 3 , BaSrTiO 3 , ZrO 2 , HfZrO 2 , HfAlO 2 , HfO 2 , and ZiTrO 2 .
7. The integrated circuit of claim 1 , wherein the ferroelectric layer has a thickness between 1 nm to 4 nm.
8. The integrated circuit of claim 1 , wherein the ferroelectric layer is between the gate electrode and each of the first and second spacers.
9. The integrated circuit of claim 1 , wherein the interfacial oxide layer includes a low-k dielectric material.
10. The integrated circuit of claim 1 , wherein the interfacial oxide layer includes oxygen and at least one of silicon, aluminum, zirconium, hafnium, lanthanum, and tantalum.
11. The integrated circuit of claim 1 , wherein the interfacial oxide layer has a thickness between 0.5 nm to 3 nm.
12. The integrated circuit of claim 1 , wherein the interfacial oxide layer is between the gate electrode and each of the first and second spacers.
13. The integrated circuit of claim 1 , wherein the gate stack, source region, the drain region are part of a planar transistor.
14. The integrated circuit of claim 1 , wherein the gate stack, source region, the drain region are part of a non-planar transistor.
15. The integrated circuit of claim 14 , wherein the transistor configuration includes a gate-all-around configuration.