Integrated device having phase interpolator and input controller thereof

1. An integrated circuit device comprising:

a sensing circuit receiving multiple input clock phases and a phase selection (PI) code and configured to determine a delay code from a plurality of delay codes using the PI code and the multiple input clock phases;

a variable delay circuit coupled to the sensing circuit and configured to:

generate a variable delay based on the delay code; and

generate a delayed PI code using the PI code and the delay code, wherein the delayed PI code corresponds to a code obtained from adding the variable delay to the PI code; and

a phase interpolator coupled to the variable delay circuit and configured to generate an output clock phase from the multiple input clock phases using the delayed PI code.

2. The integrated circuit device of claim 1 ,

wherein the plurality of delay codes represent a plurality of integer values which are determined based on time spacing between the PI code and the multiple input clock phases, and

wherein the PI code includes information to select a number of input clock phases from the multiple input clock phases, and an interpolation function to be applied on the number of input clock phases among the multiple input clock phases to generate the output clock phase.

3. The integrated circuit device of claim 1 ,

wherein the sensing circuit is further configured to:

set an initial value of the delay code by sensing a phase of the PI code with respect to at least one of the multiple input clock phases and determine if a switching instance of the PI code is present in a safe zone in which the multiple input clock phases are at the same logic level as each other;

determine a value of the delay code by controlling the initial value of the delay code;

identify a chain of safe delay codes among the plurality of delay codes, wherein safe delay codes of the chain of safe delay codes are evenly and consecutively spaced apart from each other; and

determine a centered safe delay code from the safe delay codes of the chain of safe delay codes,

wherein the centered safe delay code has a maximum symmetric margin compared to the other safe delay codes of the chain of safe delay codes, and

wherein a value of the centered safe delay code corresponds to the initial value of the delay code.

4. The integrated circuit device of claim 3 ,

wherein the sensing circuit is further configured to:

sample, for each delay code of the plurality of delay codes, the multiple input clock phases with reference to the PI code to obtain sampled values of the multiple input clock phases,

wherein the sampled values of the multiple input clock phases for each delay code of the plurality of delay codes represent logic levels of the multiple input clock phases at a switching instant of the PI code from a logic level 0 to a logic level 1;

perform a logic operation to determine if the sampled values of the multiple input clock phases for each delay code of the plurality of delay codes are at the same logic level at the switching instant of the PI code;

determine each delay code of the plurality of delay codes as a safe delay code or an unsafe delay code; and

identify the safe delay codes of the chain of safe delay codes from the plurality of delay codes after determining each delay code of the plurality of delay codes as the safe delay code or the unsafe delay code, and

wherein the sensing circuit is further configured to determine, in response to the sampled values of the multiple input clock phases for a first delay code of the plurality of delay codes being determined as not being at the same logic level, the first delay code of the plurality of delay codes as a safe code or in response to the sampled values of the multiple input clock phases for the first delay code being determined as not being at the same logic level, the first delay code as an unsafe code.

5. The integrated circuit device of claim 4 ,

wherein the switching instant of the PI code is in the safe zone for the safe delay code, and

wherein the switching instant of the PI code is in an unsafe zone, in which the multiple input clock phases are not at the same logic level as each other, for the unsafe delay code.

6. The integrated circuit device of claim 4 ,

wherein the sensing circuit is further configured to:

select an early safe delay code and a late safe delay code using the centered safe delay code;

determine an early PI code, a middle PI code, and a late PI code by delaying the PI code using the early safe delay code, the centered safe delay code, and the late safe delay code respectively;

sample the multiple input clock phases with reference to each of the early PI code, the middle PI code, and the late PI code to generate the sampled values of the multiple input clock phases at a switching instant of each of the early PI code, the middle PI code, and the late PI code from the logic level 0 to the logic level 1;

determine an early value, a middle value, and a late value based on the sampled values of the multiple input clock phases at the switching instant of early PI code, the middle PI code, and the late PI code, respectively;

generate a plurality of decision outputs based on a combination of the early value, the middle value, and the late value, wherein each of the plurality of decision outputs indicate if the centered safe delay code has to be changed towards the early safe delay code by decreasing the centered safe delay code, if the centered safe delay code has to be changed towards the late safe delay code by increasing the centered safe delay code, or if the centered safe delay code has to be retained;

perform, after generating the plurality of decision outputs, an integration operation on the plurality of decision outputs to generate a decimal value;

decode the decimal value to determine a binary code; and

add the binary code to the centered safe delay code to determine the delay code.

7. The integrated circuit device of claim 6 ,

wherein the sensing circuit is further configured to perform a modulo operation on the delay code obtained by adding the binary code to the centered safe delay code.

8. The integrated circuit device of claim 7 ,

wherein the sensing circuit is further configured to:

select the safe delay code from the chain of safe delay codes that precedes the centered safe delay code by at least one position as the early safe delay code; and

select the safe delay code from the chain of safe delay codes that follows the centered safe delay code by at least one position as the late safe delay code.

9. The integrated circuit device of claim 7 ,

wherein the sensing circuit includes a plurality of groups of samplers,

wherein the plurality of groups of samplers include a first group of samplers configured to sample the multiple input clock phases with respect to the early PI code, a second group of samplers configured to sample the multiple input clock phases with respect to the middle PI code, and a third group of samplers configured to sample the multiple input clock phases with respect to the late PI code, and

wherein each of the plurality of groups of samplers include three D flip-flops.

10. The integrated circuit device of claim 7 ,

wherein the sensing circuit is further configured to:

perform a logic operation on the sampled values of the multiple input clock phases at the switching instant of the early PI code to determine the early value, wherein the early value represents if the sampled values of the multiple input clock phases are at the same logic level or not at a switching instant of early PI code;

perform the logic operation on the sampled values of the multiple input clock phases at the switching instant of the middle PI code to determine the middle value, wherein the middle value represents if the sampled values of the multiple input clock phases are at the same logic level or not at a switching instant of middle PI code; and

perform the logic operation on the sampled values of the multiple input clock phases at the switching instant of the late PI code to determine the late value, wherein the late value represents if the sampled values of the multiple input clock phases are at the same logic level or not at a switching instant of late PI code.

11. The integrated circuit device of claim 7 ,

wherein the sensing circuit is further configured to generate the plurality of decision outputs from the early value, the middle value, and the late value using a combinational-logic table.

12. The integrated circuit device of claim 11 ,

wherein the combinational-logic table includes a plurality of decision outputs, and

wherein each of the plurality of decision outputs is mapped with a corresponding combination of the early value, the middle value, and the late value.

13. The integrated circuit device of claim 7 ,

wherein the sensing circuit is further configured to:

perform the integration operation on the plurality of decision outputs to generate the decimal value,

wherein the decimal value is a value of the plurality of decision outputs added together, and

wherein the decimal value represents a cumulative shift to be applied on the centered safe delay code.

14. The integrated circuit device of claim 8 ,

wherein the variable delay circuit is further configured to:

generate a plurality of PI delay codes by adding the variable delay to the PI code;

select at least two of the plurality of PI delay codes using the delay code; and

interpolate between at least two of the plurality of PI delayed codes using the delay code to generate the delayed PI code, and

wherein the delayed PI code is in between at least two of the plurality of PI delayed codes or the delayed PI code is same as at least one of the plurality of PI delayed codes.

15. The integrated circuit device of claim 14 ,

wherein the variable delay circuit is configured to generate the delayed PI code which includes a known phase relationship with respect to the multiple input clock phases to ensure that switching of the delayed PI code occurs in the safe zone.

16. The integrated circuit device of claim 15 ,

wherein the variable delay circuit includes:

a PI code delay generating circuit configured to generate a plurality of PI delayed codes; and

a multiplexer configured to generate the delayed PI code,

wherein the phase interpolator is configured to, in response to the delayed PI code having the switching instant in the safe zone, generate the output clock phase with zero glitches.

17. The integrated circuit device of claim 14 ,

wherein the variable delay circuit further includes a latch configured to receive the delay code and generate, in response to the plurality of PI delay codes being at the same logic level, the delayed PI code.

18. An integrated circuit device comprising:

a sensing circuit receiving multiple input clock phases and a phase selection (PI) code and configured to determine a delay code from a plurality of delay codes using the PI code and the multiple input clock phases;

a variable delay circuit coupled to the sensing circuit and configured to:

generate a variable delay based on the delay code, and

generate a delayed PI code using the PI code and the delay code, wherein the delayed PI code corresponds to a code obtained from adding the variable delay to the PI code;

a phase interpolator coupled to the variable delay circuit and configured to generate an output clock phase from the multiple input clock phases using the delayed PI code; and

an oscillatory circuit configured to generate the multiple input clock phases.

19. The integrated circuit device of claim 18 ,

wherein the plurality of delay codes represent a plurality of integer values which are determined based on time spacing between the PI code and the multiple input clock phases, and

wherein the PI code includes information to select a number of input clock phases from the multiple input clock phases, and an interpolation function to be applied on the number of input clock phases among the multiple input clock phases to generate the output clock phase.

20. An integrated circuit device comprising:

a sensing circuit configured to:

receive a plurality of delay codes,

identify a chain of safe delay codes among the plurality of delay codes,

wherein safe delay codes of the chain of safe delay codes are evenly and consecutively spaced apart from each other,

determine a centered safe delay code from the safe delay codes of the chain of safe delay codes,

perform the integration operation on the plurality of decision outputs to generate a decimal value, wherein the decimal value is a value of the plurality of decision outputs added together, and wherein the decimal value represents a cumulative shift to be applied on the centered safe delay code,

decode the decimal value to determine a binary code;

add the binary code to the centered safe delay code to determine a delay code;

a variable delay circuit coupled to the sensing circuit and configured to:

receive a phase interpolation (PI) code,

generate a variable delay based on the delay code, and generate a delayed PI code using the PI code and the delay code, wherein the delayed PI code corresponds to a code obtained from adding the variable delay to the PI code, and

a phase interpolator coupled to the variable delay circuit and configured to generate an output clock phase from a plurality of input clock phases using the delayed PI code.