Measurement sequence determination for quantum computing device

1. A computing system comprising:

a processor configured to:

identify a plurality of measurement sequences that implement a logic gate, each measurement sequence including a plurality of measurements of a quantum state of a topological quantum computing device;

for each measurement sequence of the plurality of measurement sequences that implements the logic gate and is shorter than a predetermined number of measurements, determine a respective estimated total error rate of implementing the logic gate at the quantum state using that measurement sequence; and

determine a first measurement sequence that has a lowest estimated total error rate of the plurality of measurement sequences,

wherein the topological quantum computing device is configured to implement the logic gate by applying the first measurement sequence to the quantum state.

2. The computing system of claim 1 , wherein, for each measurement sequence of the plurality of measurement sequences, the processor is configured to determine the respective estimated total error rate at least in part by:

determining an estimated weighted error rate of each measurement included in the measurement sequence; and

determining the estimated total error rate of the measurement sequence based on the plurality of estimated weighted error rates.

3. The computing system of claim 1 , wherein the processor is configured to determine the first measurement sequence at least in part by modifying a topological encoding of a computational qubit and an ancillary qubit.

4. The computing system of claim 1 , wherein the topological quantum computing device includes a plurality of Majorana zero modes (MZMs).

5. The computing system of claim 4 , wherein the topological quantum computing device includes at least one of a Majorana tetron including four MZMs, a Majorana hexon including six MZMs, or a Majorana octon including eight MZMs.

6. The computing system of claim 4 , wherein the topological quantum computing device instantiates the plurality of MZMs in a one-sided architecture or a two-sided architecture.

7. The computing system of claim 4 , wherein the processor is configured to identify the plurality of measurement sequences that implement the logic gate at least in part by identifying one or more measurement sequences that implement the logic gate multiplied by an overall Pauli operator.

8. The computing system of claim 7 , wherein the processor is further configured to track a Pauli gate correction to the logic gate when the topological quantum computing device implements the logic gate.

9. The computing system of claim 1 , wherein the topological quantum computing device is configured to implement the logic gate at least in part by performing a forced measurement of a projection operator, wherein the forced measurement includes:

performing a first measurement of a topological charge of the quantum state;

determining whether a result of the first measurement is a predetermined target value;

when the result of the first measurement is not the predetermined target value:

resetting the quantum state; and

repeating the first measurement of the topological charge.

10. The computing system of claim 9 , wherein resetting the quantum state includes repeating a second measurement that was performed prior to the first measurement in the measurement sequence.

11. The computing system of claim 9 , wherein resetting the quantum state includes measuring a plurality of topological charges including a symmetric difference of:

a first plurality of topological charges on which the first measurement was performed; and

a second plurality of topological charges on which a second measurement was performed prior to the first measurement in the measurement sequence.

12. A method for performing a quantum computation, the method comprising:

identifying a plurality of measurement sequences that implement a logic gate, each measurement sequence including a plurality of measurements of a quantum state of a topological quantum computing device;

for each measurement sequence of the plurality of measurement sequences that implements the logic gate and is shorter than a predetermined number of measurements, determining a respective estimated total error rate of implementing the logic gate at the quantum state using that measurement sequence;

determining a first measurement sequence that has a lowest estimated total error rate of the plurality of measurement sequences; and

implementing the logic gate at the topological quantum computing device by applying the first measurement sequence to the quantum state.

13. The method of claim 12 , wherein, for each measurement sequence of the plurality of measurement sequences, determining the respective estimated total error rate includes:

determining an estimated weighted error rate of each measurement included in the measurement sequence; and

determining the estimated total error rate of the measurement sequence based on the plurality of estimated weighted error rates.

14. The method of claim 12 , wherein the topological quantum computing device includes a plurality of Majorana zero modes (MZMs).

15. The method of claim 14 , wherein:

the topological quantum computing device instantiates the plurality of MZMs in a one-sided architecture or a two-sided architecture; and

the topological quantum computing device includes at least one of a Majorana tetron including MZMs, a Majorana hexon including six MZMs, or a Majorana octon including eight MZMs.

16. The method of claim 14 , wherein identifying the plurality of measurement sequences that implement the logic gate includes identifying one or more measurement sequences that implement the logic gate multiplied by an overall Pauli operator.

17. The method of claim 12 , wherein implementing the logic gate includes performing a forced measurement of a projection operator included in the logic gate, wherein the forced measurement includes:

performing a first measurement of a topological charge of the quantum state;

determining whether a result of the first measurement is a predetermined target value;

when the result of the first measurement is not the predetermined target value:

resetting the quantum state; and

repeating the first measurement of the topological charge.

18. A computing system comprising:

a processor configured to:

identify a plurality of measurement sequences that implement a logic gate, each measurement sequence including a plurality of measurements of a quantum state of a topological quantum computing device, wherein the topological quantum computing device includes a Majorana hexon including six Majorana zero modes (MZMs);

determine an estimated weighted error rate of each measurement included in each measurement sequence of the plurality of measurement sequences that implements the logic gate and is shorter than a predetermined number of measurements; and

for each measurement sequence of the plurality of measurement sequences, determine a respective estimated total error rate of the measurement sequence based on the estimated weighted error rates of the measurements included in the measurement sequence; and

determine a first measurement sequence that has a lowest estimated total error rate of the plurality of measurement sequences,

wherein the topological quantum computing device is configured to implement the logic gate by applying the first measurement sequence to the quantum state.