Techniques for storing data to enhance recovery and detection of data corruption errors
Often there are errors when reading data from computer memory. To detect and correct these errors, there are multiple types of error correction codes. Disclosed is an error correction architecture that creates a codeword having a data portion and an error correction code portion. Swizzling rearranges the order of bits and distributes the bits among different codewords. Because the data is redistributed, a potential memory error of up to N contiguous bits, where N for example equals 2 times the number of codewords swizzled together, only affects up to, at most, two bits per swizzled codeword. This keeps the error within the error detecting capabilities of the error correction architecture. Furthermore, this can allow improved error correction and detection without requiring a change to error correcting code generators and checkers.
1. An error correction code (ECC) apparatus, comprising:
a first data swizzler configured to swap bits among a plurality of data units to form a plurality of swizzled data units, wherein the swapping of bits includes exchanging bits between different data units at a same bit position;
an ECC generator configured to generate a plurality of error correction bits, at least one error correction bit of the plurality of error correction bits generated from the plurality of swizzled data units received from the first data swizzler;
an ECC swizzler configured to swap bits among the plurality of error correction bits to form a plurality of swizzled error correction bits thereby forming a plurality of swizzled codewords, wherein each swizzled codeword includes one of the plurality of data units and at least one swizzled error correction bit of the plurality of swizzled error correction bits;
a first dynamic random access memory (DRAM) area for storing the plurality of data units of the plurality of swizzled codewords;
an at least second DRAM area for storing the plurality of swizzled error correction bits of the plurality of swizzled codewords;
a second data swizzler configured to swizzle the plurality of data units of the plurality of swizzled codewords, wherein the plurality of data units are retrieved from the first DRAM area;
an ECC deswizzler configured to deswizzle the plurality of swizzled error correction bits of the plurality of swizzled code words to generate a plurality of deswizzled error correction bits; and
an ECC checker configured to check for, from an employment of the plurality of the swizzled data units from the second data swizzler and the plurality of deswizzled error correction bits from the ECC deswizzler, a single bit error condition, and/or detect a single bit error condition or double bit error condition.
2. The ECC apparatus of claim 1 , wherein the ECC swizzler is configured to swizzle the plurality of error correction bits as a (base+9)%32 pattern.
3. The ECC apparatus of claim 1 wherein the first data swizzler is configured to swizzle the data units as a (base+65)%256 pattern.
4. The ECC apparatus of claim 1 , wherein the plurality of swizzled codewords are four swizzled codewords.
5. The ECC apparatus of claim 1 , wherein the error code correction is a single error correction double error detection (SECDED) error code correction.
6. A memory controller that employs an error correction code (ECC), comprising:
a data swizzler configured to generate a plurality of swizzled data units from a plurality of data units;
an ECC generator configured to generate a plurality of error correction bits from the plurality of data units;
an ECC swizzler configured to generate a plurality of swizzled error correction bits from the plurality of error correction bits by swapping bits among the plurality of error correction bits, wherein the swapping of bits includes exchanging bits between different error correction bits at a same position thereby forming a plurality of swizzled codewords, wherein each swizzled codeword includes one of the plurality of swizzled data units and at least one swizzled error correction bit of the plurality of swizzled error correction bits;
a data deswizzler configured to deswizzle the plurality of swizzled data units stored in at least a first dynamic random access memory (DRAM) area to generate a plurality of deswizzled data units;
an ECC deswizzler configured to deswizzle the plurality of swizzled error correction bits stored in at least a second DRAM area to generate a plurality of deswizzled error correction bits; and
an ECC checker configured to correct a single bit error condition and/or detect a double bit error condition, employing both the plurality of deswizzled data units and the plurality of deswizzled error correction bits, when either of these error conditions are present.
7. The memory controller of claim 6 , wherein the ECC swizzler is configured to swizzle the plurality of error correction bits as a (base+9)%32 pattern.
8. The memory controller of claim 6 wherein the data swizzler is configured to swizzle the plurality of data units as a (base+65)%256 pattern.
9. A method, comprising:
swizzling a plurality of data units to generate a plurality of swizzled data units;
performing error correction coding on the swizzled data units to create a plurality of error correction bits;
swapping the bits among the plurality of error correction bits to generate a plurality of swizzled error correction bits, wherein the swapping of bits includes exchanging bits between different error correction bits at a same bit position;
storing the plurality of data units and the plurality of swizzled error correction bits, wherein the storing creates a plurality of swizzled codewords;
deswizzling the plurality of swizzled error correction bits of the plurality of swizzled code words to generate a plurality of deswizzled error correction bits, wherein the plurality of swizzled error correction bits was stored in and retrieved from a dynamic random access memory (DRAM);
swizzling the plurality of data units of the plurality of swizzled code words to generate a plurality of swizzled data units, wherein the plurality of data units was stored in and retrieved from the DRAM; and
performing error correction and/or error detection on the plurality of swizzled data units and the plurality of deswizzled ECC bits.
10. The method of claim 9 , further comprising deswizzling the swizzled data units to generate a plurality of deswizzled data units and conveying the plurality of deswizzled data units in response to a read request of a memory.