Brightness controllable display apparatus

1. A display apparatus comprising:

a display panel in which a plurality of pixels are arranged in m×n; and

K shift register units configured to sequentially output pulse signals having a width adjusted to adjust brightness of the display panel to m horizontal pixel lines,

wherein each of the shift register units includes:

m main flip-flops;

m−1 sub-flip-flops connected between the m main flip-flops;

a pulse signal input terminal to which one of the pulse signals, having the width adjusted according to the adjustment of the brightness of the display panel, is input;

a clock input terminal to which clock signals, input to clock terminals of the m main flip-flops and the m−1 sub-flip-flops, are input;

a duty ratio signal input terminal to which a pulse signal, having a duty ratio adjusted according to a pulse width of the signal input to the pulse signal input terminal, is input;

m AND gates each having two input terminals connected to an output terminal of each main flip-flop and the duty ratio signal input terminal and an output terminal connected to the horizontal pixel line; and

wherein the m−1 sub-flip-flops are not connected to the m AND gates.

2. The display apparatus of claim 1 , further comprising a control unit configured to perform a control such that a signal is output to each of the pulse signal input terminal, the clock input terminal, and the duty ratio signal input terminal,

wherein the control unit performs a control such that a pulse signal having a width of

(

1

⁢

H

×

a

)

+

(

1

⁢

H

×

b

2

c

)

is output to the pulse signal input terminal according to the adjustment of the brightness of the display panel, wherein a is an integer of zero or more, c is an integer of zero or more, b is an integer of zero or more and 2 c −1 or less, and 1H refers to a period of a horizontal sync signal for sequentially controlling outputs in the m horizontal pixel lines.

3. The display apparatus of claim 2 , wherein the control unit performs a control such that a signal delayed by 1H 1/2 c relative to the horizontal sync signal is output to the pulse signal input terminal.

4. The display apparatus of claim 2 , wherein the control unit performs a control such that a first clock pulse having a period of 1H and a second clock pulse spaced apart from the first clock pulse by an interval of 1H×b/2 c are repeatedly output to the clock input terminal.

5. The display apparatus of claim 4 , wherein the control unit performs a control such that a signal delayed by 1H 1/2 c relative to the horizontal sync signal is output to the clock input terminal.

6. The display apparatus of claim 2 , further comprising a bypass circuit unit configured to directly connect the m main flip-flops in response to a control signal of the control unit.

7. The display apparatus of claim 6 , wherein, when “b” is zero, the control unit outputs the control signal for directly connecting the m main flip-flops to the bypass circuit.

8. The display apparatus of claim 6 , wherein, when “a” is zero, the control unit outputs the control signal for directly connecting the m main flip-flops to the bypass circuit and performs a control such that a pulse signal having a width of 1H is output to the pulse signal input terminal.

9. The display apparatus of claim 8 , wherein the control unit performs a control such that a signal delayed by 1H×1/2 c relative to the horizontal sync signal is output to the pulse signal input terminal.

10. The display apparatus of claim 8 , wherein the control unit performs a control such that a clock pulse having a period of 1H and a length of 1H×b/2 c is repeatedly output to the clock input terminal and the duty ratio signal input terminal.

11. The display apparatus of claim 10 , wherein the control unit performs a control such that a signal delayed by 1H×1/2 c relative to the horizontal sync signal is output to the clock input terminal and the duty ratio signal input terminal.