IP Library › Granted Patent US 11,476,056
Granted Patent B2
US 11,476,056 · App. 17/065,879 · Granted Oct 18, 2022

Capacitor and method for manufacturing the same

Inventors: Hiroshi Nakagawa (Nagaokakyo, JP); Tomoyuki Ashimine (Nagaokakyo, JP); Yasuhiro Murase (Nagaokakyo, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H01G4/33H01G4/018H01L27/10829
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Quick Facts
Patent No.
US 11,476,056
App. No.
17/065,879
Granted
Oct 18, 2022
Kind
B2
Abstract

A capacitor that includes a substrate, a dielectric portion, and a conductor layer. The dielectric portion includes a thick film portion and a thin film portion. The thick film portion has a thickness larger than the average thickness of the dielectric portion in a direction perpendicular to the first main surface. The thin film portion has a thickness smaller than the average thickness of the dielectric portion in the direction perpendicular to the first main surface. The thick film portion has a larger relative permittivity than the thin film portion.

Claims (26)

1. A capacitor comprising:

a substrate including a first main surface and a second main surface opposite the first main surface;

a dielectric portion including at least one dielectric layer along the first main surface, wherein the dielectric portion includes a thick film portion having a thickness larger than an average thickness of the dielectric portion and a thin film portion having a thickness smaller than the average thickness, the average thickness being measured in a direction perpendicular to the first main surface, and the thick film portion having a larger relative permittivity than the thin film portion; and

a conductor layer on the dielectric portion.

2. The capacitor according to claim 1 , wherein

the substrate includes a recess in the first main surface,

the recess includes an upper end and a lower end,

the upper end is covered with the thick film portion, and

the lower end is covered with the thin film portion.

3. The capacitor according to claim 2 , wherein

the at least one dielectric layer is a plurality of dielectric layers,

the plurality of dielectric layers include an outermost dielectric layer closest to the conductor layer and at least one inner dielectric layer closest to the substrate, and

the outermost dielectric layer has a larger maximum layer thickness than the inner dielectric layer.

4. The capacitor according to claim 3 , wherein at least one of the plurality of dielectric layers is a doped dielectric layer containing an impurity that increases a relative permittivity of the doped dielectric layer.

5. The capacitor according to claim 4 , wherein the thick film portion in the doped dielectric layer includes a region in which a concentration of the impurity is increased where the conductor layer is closest thereto, or a region in which a concentration of the impurity is increased where the substrate is closest thereto, in a direction perpendicular to the first main surface.

6. The capacitor according to claim 5 , wherein the concentration of the impurity is increased where the conductor layer is closest thereto in the direction perpendicular to the first main surface in the thick film portion in the doped dielectric layer.

7. The capacitor according to claim 1 , wherein

the at least one dielectric layer is a plurality of dielectric layers,

the plurality of dielectric layers include an outermost dielectric layer closest to the conductor layer and at least one inner dielectric layer closest to the substrate, and

the outermost dielectric layer has a larger maximum layer thickness than the inner dielectric layer.

8. The capacitor according to claim 7 , wherein at least one of the plurality of dielectric layers is a doped dielectric layer containing an impurity that increases a relative permittivity of the doped dielectric layer.

9. The capacitor according to claim 8 , wherein the thick film portion in the doped dielectric layer includes a region in which a concentration of the impurity is increased where the conductor layer is closest thereto, or a region in which a concentration of the impurity is increased where the substrate is closest thereto, in a direction perpendicular to the first main surface.

10. The capacitor according to claim 9 , wherein the concentration of the impurity is increased where the conductor layer is closest thereto in the direction perpendicular to the first main surface in the thick film portion in the doped dielectric layer.

11. The capacitor according to claim 1 , wherein the at least one dielectric layer is a doped dielectric layer containing an impurity that increases a relative permittivity of the doped dielectric layer.

12. The capacitor according to claim 11 , wherein the thick film portion in the doped dielectric layer includes a region in which a concentration of the impurity is increased where the conductor layer is closest thereto, or a region in which a concentration of the impurity is increased where the substrate is closest thereto, in a direction perpendicular to the first main surface.

13. The capacitor according to claim 12 , Wherein the concentration of the impurity is increased where the conductor layer is closest, thereto in the direction perpendicular to the first main surface in the thick film portion in the doped dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2020
From: NAKAGAWA, HIROSHI; ASHIMINE, TOMOYUKI; MURASE, YASUHIRO
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 054009/0378 →
Priority Claims (1)
JP JP2018-114893 · Jun 15, 2018 · national
Continuity (2)
Continuation PCTJP2019019907 · May 20, 2019
Related Publication 20210027950A1 · Jan 28, 2021
Cited By (1)
US 12,621,933