IP Library › Granted Patent US 11,476,262
Granted Patent B2
US 11,476,262 · App. 16/941,174 · Granted Oct 18, 2022

Methods of forming an array of capacitors

Inventors: Fatma Arzum Simsek-Ege (Boise, ID); Durai Vishak Nirmal Ramaswamy (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/11507H01L21/7688H01L27/10814H01L27/10855H01L27/11504H01L28/55
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Quick Facts
Patent No.
US 11,476,262
App. No.
16/941,174
Granted
Oct 18, 2022
Kind
B2
Abstract

A method of forming an array of capacitors comprises forming rows and columns of horizontally-spaced openings in a sacrificial material. Fill material is formed in multiple of the columns of the openings and lower capacitor electrodes a are formed in a plurality of the columns that are between the columns of the openings comprising the fill material therein. The fill material is of different composition from that of the lower capacitor electrodes. The fill material is between a plurality of horizontally-spaced groups that individually comprises the lower capacitor electrodes. Immediately-adjacent of the groups are horizontally spaced apart from one another by a gap that comprises at least one of the columns of the openings comprising the fill material therein. The sacrificial material is removed to expose laterally-outer sides of the lower capacitor electrodes. A capacitor insulator is formed over tops and the laterally-outer sides of the lower capacitor electrodes. Upper capacitor electrode material is formed over the capacitor insulator and the lower capacitor electrodes. A horizontally-elongated conductive line is formed atop individual of the groups that directly electrically couple together the upper capacitor electrode material there-below in that individual group.

Claims (28)

1. A method of forming an array of capacitors, comprising:

forming rows and columns of horizontally-spaced openings in a sacrificial material;

forming fill material in multiple of the columns of the openings with a remainder of the openings being free of the fill material, the fill material entirely filling the openings comprised by the multiple of the columns of the openings;

forming lower capacitor electrodes in a plurality of the columns that are between the columns of the openings comprising the fill material therein, the fill material being of different composition from that of the lower capacitor electrodes, the fill material being between a plurality of horizontally-spaced groups individually comprising the lower capacitor electrodes, immediately-adjacent of the groups being horizontally spaced apart from one another by a gap that comprises at least one of the columns of the openings comprising the fill material therein;

removing the sacrificial material to expose laterally-outer sides of the lower capacitor electrodes;

forming a capacitor insulator over tops and the laterally-outer sides of the lower capacitor electrodes;

forming upper capacitor electrode material over the capacitor insulator and the lower capacitor electrodes; and

forming a horizontally-elongated conductive line atop individual of the groups that directly electrically couples together the upper capacitor electrode material there-below in that individual group.

2. The method of claim 1 wherein the fill material is formed before the lower capacitor electrodes are formed.

3. The method of claim 1 wherein the fill material comprises a different composition from that of the sacrificial material.

4. The method of claim 3 wherein the removing the sacrificial material is conducted selectively relative to the fill material.

5. The method of claim 4 wherein the fill material remains in a finished construction.

6. The method of claim 1 wherein the fill material and the sacrificial material are of the same composition relative one another, the act of removing the sacrificial material also removing the fill material.

7. The method of claim 1 wherein the capacitor insulator is ferroelectric.

8. The method of claim 1 comprising forming a plurality of transistors that individually directly electrically couple to individual of the lower capacitor electrodes.

9. The method of claim 8 wherein the transistors are vertical transistors.

10. A method of forming an array of capacitors, comprising:

forming rows and columns of horizontally-spaced openings in a substrate;

forming fill material in multiple of the columns of the openings to form pillars of the fill material that entirely fill the openings in the multiple columns and forming lower capacitor electrodes in a plurality of the columns that are between the pillars, the fill material being of different composition from that of the lower capacitor electrodes, the pillars being between a plurality of horizontally-spaced groups individually comprising the lower capacitor electrodes, immediately-adjacent of the groups being horizontally spaced apart from one another by a gap that comprises at least one of the columns of the pillars;

forming a capacitor insulator over the lower capacitor electrodes and the pillars;

forming upper capacitor electrode material over the capacitor insulator, the lower capacitor electrodes, and the pillars; the upper capacitor electrode material extending across the gap and connecting the upper capacitor electrode material that is in the immediately-adjacent groups; and

removing at least a portion of the upper capacitor electrode material from the gap to disconnect the upper capacitor electrode material from being connected between the immediately-adjacent groups and forming a horizontally-elongated conductive line atop individual of the groups that directly electrically couples together the upper capacitor electrode material there-below in that individual group.

11. The method of claim 10 wherein the immediately-adjacent groups are horizontally spaced farther apart than are closest-immediately-adjacent of the lower capacitor electrodes within the groups.

12. The method of claim 10 wherein the openings are formed in a sacrificial material that comprises a different composition from that of the fill material, and further comprising:

removing the sacrificial material to expose laterally-outer sides of the lower capacitor electrodes, the capacitor insulator and the upper capacitor electrode material being formed over the laterally-outer sides of the lower capacitor electrodes.

13. The method of claim 10 wherein the capacitor insulator is ferroelectric.

14. The method of claim 10 comprising forming a plurality of transistors that individually directly electrically couple to individual of the lower capacitor electrodes.

15. The method of claim 14 wherein the transistors are vertical transistors.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2021
From: SIMSEK-EGE, FATMA ARZUM; RAMASWAMY, DURAI VISHAK NIRMAL
To: MICRON TECHNOLOGY, INC.
Reel/Frame 057123/0272 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2020
From: SIMSEK-EGE, FATMA ARZUM; RAMASWAMY, DURAI VISHAK NIRMAL
To: MICRON TECHNOLOGY, INC.
Reel/Frame 053332/0305 →
Continuity (1)
Related Publication 20220037342A1 · Feb 3, 2022