Three-dimensional semiconductor device

1. A three-dimensional semiconductor device comprising:

a stack structure on a lower structure and including interlayer insulation layers and gate horizontal patterns alternately stacked in a vertical direction, the vertical direction being perpendicular to an upper surface of the lower structure, the gate horizontal patterns being spaced apart from each other by a first interval in the vertical direction, the interlayer insulation layers being spaced apart from each other by a second interval in the vertical direction;

a vertical channel structure passing through the stack structure in the vertical direction and including a channel semiconductor layer; and

a first vertical support structure passing through the stack structure in the vertical direction and spaced apart from the vertical channel structure in a horizontal direction,

wherein a cross-sectional shape in the vertical direction of the vertical channel structure is different from a cross-sectional shape in the vertical direction of the first vertical support structure,

wherein the vertical channel structure includes a first vertical region, a second vertical region, and a width variation portion between the first vertical region and the second vertical region,

wherein an intermediate interlayer insulation layer of the interlayer insulation layers spaced apart from each other by the second interval is adjacent to the width variation portion,

wherein a lower surface of the intermediate interlayer insulation layer contacts an upper surface of the width variation portion, and

wherein the intermediate interlayer insulation layer and an interlayer insulation layer adjacent to the intermediate interlayer insulation layer in the vertical direction, among the interlayer insulation layers, have the same thickness.

2. The three-dimensional semiconductor device according to claim 1 , wherein:

the first vertical region comprises a lower region and an upper region on the lower region,

the second vertical region comprises a lower region and an upper region on the lower region,

the upper region of the first vertical region has a width greater than a width of the lower region of the first vertical region, and

the upper region of the second vertical region has a width greater than a width of the lower region of the second vertical region.

3. The three-dimensional semiconductor device according to claim 2 , wherein:

the upper region of the first vertical region adjacent to the second vertical region has a first width,

the lower region of the second vertical region adjacent to the first vertical region has a second width less than the first width, and

the width variation portion is a portion that changes from the first width to the second width between the upper region of the first vertical region and the lower region of the second vertical region.

4. The three-dimensional semiconductor device according to claim 1 , wherein:

each of the first vertical region and the second vertical region changes in width with regularity in the vertical direction as they extend away from the lower structure,

an upper region of the first vertical region and a lower region of the second vertical region have widths different from each other, and

the width variation portion is a portion that changes in width between the upper region of the first vertical region and a lower region of the second vertical region.

5. The three-dimensional semiconductor device according to claim 4 , wherein the first vertical support structure changes in width with regularity in the vertical direction away from the lower structure.

6. The three-dimensional semiconductor device according to claim 1 , further comprising:

a second vertical support structure spaced apart from the vertical channel structure and the first vertical support structure; and

a contact plug contacting an upper surface of the vertical channel structure,

wherein the second vertical support structure has the same cross-sectional structure in the vertical direction as the vertical channel structure.

7. The three-dimensional semiconductor device according to claim 1 ,

wherein the vertical channel structure contacts the lower structure,

wherein the first vertical support structure contacts the lower structure, and

wherein a lower end of the vertical support structure and a lower end of the vertical channel structure are at a lower level than the upper surface of lower structure.

8. The three-dimensional semiconductor device according to claim 1 ,

wherein the vertical channel structure includes an insulating core pattern, a channel semiconductor layer on a side surface of the insulating core pattern, and a data storage layer on an external surface of the channel semiconductor layer,

wherein the first vertical support structure does not include a material of the channel semiconductor layer,

wherein a first gate horizontal pattern among the gate horizontal patterns is a lowermost word line among word lines, and a second gate horizontal pattern among the gate horizontal patterns is an uppermost word line among the word lines,

wherein at least a portion of the channel semiconductor layer extends continuously from a first height level to a second height level,

wherein the first height level is at a lower level than the first gate horizontal pattern, and

wherein the second height level is at a higher level than the second gate horizontal pattern.

9. The three-dimensional semiconductor device according to claim 8 , wherein the width variation portion of the vertical channel structure is a junction region between the first vertical region of the vertical channel structure and the second vertical region of the vertical channel structure,

wherein the first vertical support structure is formed of a silicon oxide layer, and

wherein the silicon oxide layer of the first vertical support structure extends continuously from the first height level to the second height level.

10. The three-dimensional semiconductor device according to claim 1 , wherein an upper surface of the first vertical support structure is at a higher level than an upper surface of the vertical channel structure.

11. A three-dimensional semiconductor device, comprising:

a stack structure on a lower structure and including interlayer insulation layers and gate horizontal patterns alternately stacked in a vertical direction, the vertical direction being perpendicular to an upper surface of the lower structure;

a vertical channel structure passing through the stack structure in the vertical direction and including a channel semiconductor layer;

a first vertical support structure passing through the stack structure in the vertical direction and spaced apart from the vertical channel structure in a horizontal direction;

separation structures;

protection patterns; and

a buffer horizontal pattern,

wherein a cross-sectional shape in the vertical direction of the vertical channel structure is different from a cross-sectional shape in the vertical direction of the first vertical support structure,

wherein the vertical channel structure includes a first vertical region, a second vertical region, and a width variation portion between the first vertical region and the second vertical region,

wherein the interlayer insulation layers include an intermediate interlayer insulation layer adjacent to the width variation portion,

wherein a lower surface of the intermediate interlayer insulation layer contacts an upper surface of the width variation portion, and

wherein the intermediate interlayer insulation layer and an interlayer insulation layer adjacent to the intermediate interlayer insulation layer in the vertical direction, among the interlayer insulation layers, have the same thickness,

wherein the gate horizontal patterns are disposed between the separation structures,

wherein the gate horizontal patterns comprise first gate horizontal patterns and second gate horizontal patterns on the first gate horizontal patterns,

wherein the buffer horizontal pattern is disposed between an uppermost first gate horizontal pattern among the first gate horizontal patterns and a lowermost second gate horizontal pattern among the second gate horizontal patterns, and is formed of a material different from a material of the gate horizontal patterns,

wherein the buffer horizontal pattern is between the intermediate interlayer insulation layer and the uppermost first gate horizontal pattern, and

wherein the protection patterns are disposed between the separation structures and the buffer horizontal pattern, and are formed of a material different from the material of the buffer horizontal pattern.

12. The three-dimensional semiconductor device according to claim 11 , wherein:

the gate horizontal patterns are formed of a conductive material,

the buffer horizontal pattern is formed of an insulating material, and

the protection patterns are formed of an insulating material different from the insulating material of the buffer horizontal pattern.

13. A three-dimensional semiconductor device, comprising:

a stack structure disposed on a lower structure and including interlayer insulation layers and gate horizontal patterns alternately stacked in a vertical direction, the vertical direction being perpendicular to an upper surface of the lower structure, the gate horizontal patterns being spaced apart from each other by a first interval in the vertical direction, the interlaying insulation layers being spaced apart from each other by a second interval in the vertical direction;

a vertical channel structure passing through the stack structure in the vertical direction;

a first vertical support structure passing through the stack structure in the vertical direction and spaced apart from the vertical channel structure; and

a second vertical support structure passing through the stack structure in the vertical direction,

wherein the first vertical support structure and the vertical channel structure have cross-sectional structures different from each other in the vertical direction,

wherein the first and second vertical support structures have cross-sectional structures different from each other in the vertical direction,

wherein the vertical channel structure comprises a first vertical region, a second vertical region, and a width variation portion between the first vertical region and the second vertical region, and

wherein the interlayer insulation layers spaced apart from each other by the second interval include an interlayer insulation layer having a lower surface that contacts an upper surface of the width variation portion.

14. The three-dimensional semiconductor device according to claim 13 ,

wherein an upper surface of the second vertical support structure is coplanar with an upper surface of the vertical channel structure.

15. The three-dimensional semiconductor device according to claim 14 ,

wherein the vertical channel structure and the second vertical support structure have the same cross-sectional structure as each other and the same width as each other, and

wherein the vertical channel structure further comprises a channel semiconductor layer.

16. The three-dimensional semiconductor device according to claim 13 , further comprising:

separation structures;

protection patterns; and

a buffer horizontal pattern,

wherein the gate horizontal patterns are disposed between the separation structures,

wherein the gate horizontal patterns comprise first intermediate gate horizontal patterns and second intermediate gate horizontal patterns on the first intermediate gate horizontal patterns,

wherein the buffer horizontal pattern is disposed between the first intermediate gate horizontal patterns and the second intermediate gate horizontal patterns, and is formed of a material different from a material of the gate horizontal patterns, and

wherein the protection patterns are disposed between the separation structures and the buffer horizontal pattern, and are formed of a material different from the material of the buffer horizontal pattern.

17. The three-dimensional semiconductor device according to claim 16 , further comprising:

additional dielectric layers between the gate horizontal patterns and the interlayer insulation layers,

wherein a thickness of the buffer horizontal pattern is greater than a thickness of each of the gate horizontal patterns.

18. The three-dimensional semiconductor device according to claim 13 ,

wherein the vertical channel structure includes an insulating core pattern, a channel semiconductor layer on a side surface of the insulating core pattern, and a data storage layer on an external surface of the channel semiconductor layer,

wherein the first vertical support structure does not include a material of the channel semiconductor layer,

wherein a first gate horizontal pattern among the gate horizontal patterns is a lowermost word line among word lines, and a second gate horizontal pattern among the gate horizontal patterns is an uppermost word line among the word lines,

wherein at least a portion of the channel semiconductor layer extends continuously from a first height level to a second height level,

wherein the first height level is at a lower level than the first gate horizontal pattern, and

wherein the second height level is at a higher level than the second gate horizontal pattern.

19. The three-dimensional semiconductor device according to claim 18 , wherein the width variation portion of the vertical channel structure is a junction region between the first vertical region of the vertical channel structure and the second vertical region of the vertical channel structure,

wherein the first vertical support structure is formed of a silicon oxide layer, and

wherein the silicon oxide layer of the first vertical support structure extends continuously from the first height level to the second height level.

20. The three-dimensional semiconductor device according to claim 13 , wherein an upper surface of the first vertical support structure is at a higher level than an upper surface of the vertical channel structure.