Semiconductor device and method of manufacturing thereof
There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.
1. A semiconductor device comprising:
a first semiconductor element comprising:
a first electrode;
a first metal layer disposed in a first concave shape in contact with and above the first electrode, the first metal layer comprising a nitride film of a vanadium group metal;
a second metal layer disposed in a second concave shape in contact with and above the first metal layer, wherein the second metal layer is made of the vanadium group metal;
a third metal layer disposed in a flat shape in contact with the second metal layer; and
a passivation layer disposed above and in contact with a top-facing side of each of the first metal layer and the second metal layer;
a second semiconductor element; and
a micro-solder bump in contact with the passivation layer, the third metal layer, and the second semiconductor element, wherein the micro-solder bump is disposed directly on the third metal layer, and wherein the third metal layer is exposed through an opening in the passivation layer.
2. The semiconductor device according to claim 1 , wherein the second metal layer and the third metal layer are sequentially formed on a concave bump pad, and wherein the third metal layer is diffused to the micro-solder bump.
3. The semiconductor device according to claim 2 , wherein the first semiconductor element has a plurality of concave bump pads thereon.
4. The semiconductor device according to claim 3 , wherein diameters of each of the concave bump pads differ depending on a usage of an electrode connected thereto.
5. The semiconductor device according to claim 2 , wherein a diameter of the micro-solder bump corresponds to a diameter of the concave bump pad.
6. The semiconductor device according to claim 2 , wherein the first metal layer is sequentially formed on the concave bump pad together with the second metal layer and the third metal layer, and wherein the third metal layer is closest to the micro-solder bump.
7. The semiconductor device according to claim 6 , wherein the second metal layer has an average thickness of 30 nanometers or greater.
8. The semiconductor device according to claim 6 , wherein the first metal layer has an average thickness of 10 nanometers or greater.
9. The semiconductor device according to claim 6 , wherein the second metal layer is Ta, and the first metal layer is TaN.
10. The semiconductor device according to claim 6 , wherein the third metal layer is one of Cu, Co, Ni, Pd, Au, and Pt.
11. The semiconductor device according to claim 1 , wherein the first electrode is a through-electrode.
12. The semiconductor device according to claim 1 , further comprising: an opening portion that extends from a surface of the first semiconductor element to a metal wiring in the first semiconductor element, wherein the opening portion forms a concave bump pad.
13. The semiconductor device according to claim 1 , wherein the semiconductor device is a stacked CMOS image sensor including a logic chip equivalent to the second semiconductor element that is CoW-connected to a pixel substrate equivalent to the first semiconductor element.
14. The semiconductor device according to claim 1 , wherein the micro-solder bump comprises Sn.
15. The semiconductor device according to claim 1 , wherein the third metal layer is diffused to the micro-solder bump.
16. The semiconductor device according to claim 15 , wherein the micro-solder bump is in contact with a side surface of the passivation layer.
17. The semiconductor device according to claim 1 , wherein the second metal layer is Ta, and the first metal layer is TaN.
18. The semiconductor device according to claim 1 , wherein the second metal layer has an average thickness of 30 nanometers or greater.
19. The semiconductor device according to claim 1 , wherein the first metal layer has an average thickness of 10 nanometers or greater.
20. A method of manufacturing a semiconductor device including a first semiconductor element, the first semiconductor element having a first electrode, and a second semiconductor element, the method comprising:
disposing a first metal layer in a first concave shape in contact with and above the first electrode, the first metal layer comprising a nitride film of a vanadium group metal;
disposing a second metal layer in a second concave shape in contact with and above the first metal layer, wherein the second metal layer is made of the vanadium group metal;
disposing a third metal layer in a flat shape in contact with the second metal layer;
disposing a passivation layer above and in contact with a top-facing side of each of the first and second metal layers; and
disposing a micro-solder bump on the third metal layer, wherein the micro-solder bump is in contact with the passivation layer, the third metal layer, and the second semiconductor element, and wherein the third metal layer is exposed through an opening in the passivation layer.
21. The method according to claim 20 , wherein the first semiconductor element has a plurality of concave bump pads thereon.
22. The method according to claim 20 , wherein the second metal layer has an average thickness of 30 nanometers or greater.
23. The method according to claim 20 , wherein the first metal layer has an average thickness of 10 nanometers or greater.
24. The method according to claim 20 , wherein the second metal layer is Ta, and the first metal layer is TaN.
25. The method according to claim 20 , wherein the first electrode is a through-electrode.
26. The method according to claim 20 , wherein the semiconductor device comprises an opening portion that extends from a surface of the first semiconductor element to a metal wiring in the first semiconductor element, wherein the opening portion forms a concave bump pad.