Ultra-dense array of LEDs with half cavities and reflective sidewalls, and hybrid bonding methods
In one approach, an LED array uses a combination of a half cavity and straight reflective sidewalls to improve the power distribution so that more light falls within the collection angle of the projection optics. From the bottom upwards, the LEDs in the array include a reflector, a thinner p-layer and a thicker n-layer. An active region (such as quantum wells) between the p-layer and the p-layer generates light. Without additional structures, the generated light would have an isotropic distribution and not much of the light would fall within the collection angle of the projection optics. However, the bottom reflector and p-layer form a half cavity for the light emitted from the active region. This alters the angular power distribution. Straight reflective sidewalls extending from the active region upwards into the n-layer further reflect light from the altered power distribution into the collection angle of the projection optics.
1. A method for manufacturing an image source comprising an LED frontplane and a pixel driver backplane, the method comprising:
manufacturing an LED frontplane having an array of LEDs, comprising:
at least partially filling trenches in an LED frontplate with a dielectric; wherein:
the LED frontplate comprises, in order from bottom to top: a bottom layer that is one of an n-layer and a p-layer, an active region, a top layer that is the other of an n-layer and a p-layer, and a reflector layer;
the trenches extend through the reflector layer, the top layer, the active region and into the bottom layer; and
the trenches isolate active regions of adjacent individual LEDs;
planarizing the LED frontplane to produce a top surface comprising the planarized dielectric and reflector layer;
forming an oxide layer on the top surface; and
creating metal plugs through the oxide layer and contacting the reflector layer of individual LEDs;
manufacturing a pixel driver backplane comprising contacts for an array of pixel drivers, comprising;
forming an oxide layer on a flat surface comprising the contacts; and
creating metal plugs through the oxide layer and contacting the contacts; and
hybrid bonding the LED frontplane with the pixel driver backplane, wherein the oxide layers from the LED frontplane and the pixel driver backplane form an oxide-oxide bonding and the metal plugs from the LED frontplane and the pixel driver backplane form a metal-metal bonding.
2. The method of claim 1 wherein hybrid bonding the LED frontplane with the pixel driver backplane comprises:
aligning the metal plugs from the LED frontplane with the metal plugs from the pixel driver backplane;
bonding the oxide layers from the LED frontplane and the pixel driver backplane, wherein the metal plugs from the LED frontplane and the pixel driver backplane are aligned but do not contact each other;
increasing a temperature of the metal plugs, whereby the metal plugs from the LED frontplane and the pixel driver backplane expand and contact each other and bond to each other.
3. The method of claim 1 wherein the metal plugs from the LED frontplane have an aspect ratio of height to width of not less than 4:1.
4. The method of claim 3 wherein creating the metal plugs for the LED frontplane comprises:
plasma etching vias through the oxide layer to the reflectors; and
filling the vias with the metal plugs.
5. The method of claim 3 wherein a pitch between the LEDs in the array is not greater than 3 um, and the trenches have an aspect ratio of height to width of not less than 1:1.
6. The method of claim 1 wherein hybrid bonding the LED frontplane with the pixel driver backplane comprises a wafer-wafer bonding of a wafer containing multiple LED frontplanes with a separate wafer containing multiple pixel driver backplanes.
7. The method of claim 1 wherein hybrid bonding the LED frontplane with the pixel driver backplane comprises a wafer-die bonding of a wafer containing multiple LED frontplanes with a die containing the pixel driver backplane.
8. The method of claim 1 wherein hybrid bonding the LED frontplane with the pixel driver backplane comprises a die-die bonding of a die containing the LED frontplane with a separate die containing the pixel driver backplane.
9. The method of claim 1 wherein the LED frontplane has a topography of at least 1 um before planarization, and the topography is reduced to less than 0.2 um by the planarization.
10. The method of claim 1 wherein manufacturing the LED frontplane further comprises:
creating a wafer with the bottom layer, the active region, the top layer, and the reflector layer; and
etching the trenches through the reflector layer, the top layer, the active region and into the bottom layer.
11. The method of claim 1 wherein manufacturing the LED frontplane further comprises:
growing the bottom layer, the active region, the top layer, and the reflector layer on a wafer, wherein the layers are grown in a pattern that forms the trenches.
12. An image source comprising:
an LED frontplane comprising:
an array of LEDs, the LEDs comprising:
a semiconductor stack comprising a bottom layer that is one of an n-layer and a p-layer, a top layer that is the other of an n-layer and a p-layer, and an active region between the bottom layer and the top layer; and
a bottom reflector below the bottom layer;
trenches extending through the bottom reflectors; and
an oxide layer below the bottom reflectors, and an array of metal plugs through the oxide layer and contacting the bottom reflectors; and
a pixel driver backplane comprising:
an array of pixel drivers with contacts to pixel drivers; and
an oxide layer with an array of metal plugs through the oxide layer and contacting the contacts to the pixel drivers; wherein the oxide layer and metal plugs from the pixel driver backplane are bonded to the oxide layer and metal plugs from the LED frontplane.
13. The image source of claim 12 wherein the metal plugs from the LED frontplane have an aspect ratio of height to width of not less than 4:1.
14. The image source of claim 12 wherein a pitch between the LEDs in the array is not greater than 3 um, and a combined thickness of the oxide layers from the LED frontplane and the pixel driver backplane is not less than 4 um.
15. The image source of claim 12 wherein each LED is individually connected to a corresponding pixel driver by one of the metal plugs on the LED frontplane bonded to the corresponding metal plug on the pixel driver backplane.
16. The image source of claim 12 wherein the array of LEDs comprises an array of at least 200×200 LEDs, and the LED frontplane and pixel driver backplane each have an area of not more than 2 mm×2 mm.
17. The image source of claim 12 wherein the bottom reflector and bottom layer form a half cavity for light emitted from the active region.
18. The image source of claim 17 wherein the LEDs further comprise:
reflective sidewalls extending from the active region upwards and adjacent to the top layer, wherein the half cavity redistributes light emitted from the active region into an angular power distribution with at least one lobe, and the reflective sidewalls reflect at least one of the lobes to a direction that is closer to normal to the active region.
19. The image source of claim 18 wherein the reflective sidewalls are straight, reflective sidewalls with a ratio of a height of the sidewall compared to the pitch of the LED array of at least 2:1.
20. The image source of claim 12 wherein the LED frontplane comprises an array of GaN LEDs and the pixel drive backplane comprises an array of CMOS pixel drivers.