IP Library › Granted Patent US 11,476,411
Granted Patent B2
US 11,476,411 · App. 17/204,961 · Granted Oct 18, 2022

Semiconductor device and method for fabricating the same

Inventors: Chen-Yi Weng (New Taipei, TW); Jing-Yin Jhang (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L43/02H01F10/3254H01F41/34H01L21/7684H01L21/76802H01L21/76877H01L23/528H01L23/5226H01L27/222H01L43/12H01L43/10
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Quick Facts
Patent No.
US 11,476,411
App. No.
17/204,961
Granted
Oct 18, 2022
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a liner on the MTJ; removing part of the liner to form a recess exposing the MTJ; and forming a conductive layer in the recess, wherein top surfaces of the conductive layer and the liner are coplanar. Preferably the MTJ further includes: a bottom electrode on the substrate, a fixed layer on the bottom electrode, and a top electrode on the fixed layer, in which the conductive layer and the top electrode are made of same material.

Claims (27)

1. A method for fabricating semiconductor device, comprising:

forming a first inter-metal dielectric (IMD) on a substrate;

forming a first metal interconnection in the first IMD layer;

forming a first electrode layer, a fixed layer, and a second electrode layer on the first metal interconnection and the first IMD layer;

patterning the first electrode layer, the fixed layer, and the second electrode layer to form a MTJ comprising a bottom electrode and a top electrode, wherein a width of the top electrode is equal to a width of the fixed layer;

forming a liner on the top electrode;

removing part of the liner to form a recess exposing the top electrode; and

forming a conductive layer in the recess, wherein a top surface of the conductive layer is even with a top surface of the liner.

2. The method of claim 1 , further comprising:

forming the MTJ on the first metal interconnection;

forming a spacer around the MTJ;

forming a second IMD layer on the first IMD layer and around the spacer; and

forming the liner on the second IMD layer, the spacer, and the MTJ.

3. The method of claim 2 , further comprising:

removing part of the liner to form a recess exposing the MTJ, the spacer, and part of the second IMD layer;

forming the conductive layer in the recess; and

planarizing part of the conductive layer so that top surfaces of the conductive layer and the liner are coplanar.

4. The method of claim 2 , further comprising forming a second metal interconnection in the second IMD layer and adjacent to the MTJ before forming the liner.

5. The method of claim 4 , wherein top surfaces of the second metal interconnection and the second IMD layer are coplanar.

6. The method of claim 2 , wherein the MTJ comprises:

the bottom electrode on the first metal interconnection;

the fixed layer on the bottom electrode; and

the top electrode on the fixed layer.

7. The method of claim 6 , wherein the conductive layer and the top electrode comprise a same material.

8. The method of claim 6 , wherein the top electrode comprises:

a bottom portion in the second IMD layer; and

a top portion in the liner.

Priority Claims (1)
CN 201811044897.2 · Sep 7, 2018 · national
Continuity (2)
Division 16166173 · Oct 22, 2018
Related Publication 20210202828A1 · Jul 1, 2021