Radiation hardened by design CMOS crystal oscillator for readout telemetry
View Patent ↗A clock source includes a comparator having a positive comparator input, a negative comparator input, a proportional to absolute temperature (PTAT) PMOS bias input, a PTAT NMOS bias input, and a comparator output, a resonator element, series and feedback resistors and other passive components coupled between the comparator output and the negative comparator input to generate a signal with approximately constant gain and frequency at the comparator output, and a PTAT bias circuit coupled to the comparator's PTAT PMOS and NMOS bias inputs, and configured to drive the PTAT PMOS bias input and the PTAT NMOS bias input to maintain approximately constant gain and frequency over the operating temperature range of the clock source.
1. A clock source comprising:
a comparator having a positive comparator input, a negative comparator input, a proportional to absolute temperature (PTAT) PMOS bias input, a PTAT NMOS bias input, and a comparator output;
a resonator element and series resistor coupled between the comparator output and the negative comparator input to generate a gain and frequency at the comparator output;
a feedback resistor between the comparator output and negative comparator input to provide a DC path for linearizing the gain of the comparator; and
a PTAT bias circuit coupled to the PTAT PMOS bias input and the PTAT NMOS bias input, and configured to drive the PTAT PMOS bias input and the PTAT NMOS bias input to maintain the gain and frequency approximately constant over an operating temperature of the clock source.
2. The clock source of claim 1 , wherein the positive comparator input is configured to be driven to compensate for radiation induced input offset.
3. The clock source of claim 1 , wherein the positive comparator input is configured to be driven to adjust a pulse width or duty cycle of the comparator output.
4. The clock source of claim 1 , wherein the resonator comprises an LC tank circuit or a piezo-electric crystal.
5. The clock source of claim 1 , wherein the PTAT PMOS bias input and the PTAT NMOS bias input are coupled to current sources in the comparator and the PTAT bias circuit is configured to provide current to the current sources that varies with temperature.
6. A method of generating a clock signal using a comparator having a positive comparator input, a negative comparator input, a proportional to absolute temperature (PTAT) PMOS bias input, a PTAT NMOS bias input, and a comparator output, the method comprising:
coupling a resonator element and series resistor between the comparator output and the negative comparator input to generate a clock signal at the comparator output; and
a feedback resistor between the comparator output and the comparator negative input to provide a DC path for linearizing gain of the comparator; and
coupling a PTAT bias circuit to the PTAT PMOS bias input and the PTAT NMOS bias input, the PTAT bias circuit configured to drive the PTAT PMOS bias input and the PTAT NMOS bias input to maintain an approximately constant gain and frequency of the clock signal over an operating temperature range of the clock source.
7. The method of claim 6 , comprising configuring the positive comparator input to be driven to compensate for radiation induced input offset.
8. The method of claim 6 , comprising configuring the positive comparator input to be driven to adjust a pulse width or duty cycle of the comparator output.
9. The method of claim 6 , wherein the resonator comprises an LC tank circuit or a piezo-electric crystal.
10. The method of claim 6 , comprising coupling the PTAT PMOS bias input and the PTAT NMOS bias input to current sources in the comparator and configuring the PTAT bias circuit to provide current to the current sources that varies with temperature.