Granted Patent B2

US 12,712,491 · App. 19/034,947 · Granted Aug 18, 2026

Inventors: James Francis Imbornone (Methuen, MA); Kheng Chong Tran (Lowell, MA); William Edward Moore (Austin, TX); Preetham Narayana Reddy (Los Angeles, CA); Dinesh Babu Mugunthu Maheswaran (Nashua, NH)

Assignee: SKYWORKS SOLUTIONS, INC.

H03B5/364H03B5/06H03B5/24H03B2200/0012H03B2200/009

Abstract

Claims (31)

1 . A crystal oscillator comprising:

a crystal;

an inverter having an input connected to a first terminal of the crystal and an output connected to a second terminal of the crystal, the inverter including an n-type metal oxide semiconductor transistor and a p-type metal oxide semiconductor transistor configured to invert an input oscillation signal from the crystal; and

a back gate bias control circuit configured to adjust a negative resistance of the inverter by controlling a body bias of at least one of the n-type metal oxide semiconductor transistor or the p-type metal oxide semiconductor transistor, the back gate bias control circuit including a first body resistor connected between a body and a source of one of the n-type metal oxide semiconductor transistor or the p-type metal oxide semiconductor transistor, and a first controllable current source configured to provide a first current to the first body resistor.

2 . The crystal oscillator of claim 1 wherein the back gate bias control circuit controls a body bias of both the n-type metal oxide semiconductor transistor and the p-type metal oxide semiconductor transistor.

3 . The crystal oscillator of claim 1 wherein the back gate bias control circuit sets the back gate bias to a first level during startup of the crystal oscillator and to a second level during steady state operation of the crystal oscillator.

4 . The crystal oscillator of claim 1 wherein the back gate bias control circuit further includes a first bypass switch connected in parallel with the first body resistor.

5 . The crystal oscillator of claim 1 wherein the back gate bias control circuit further includes a first filtering capacitor connected in parallel with the first body resistor.

6 . The crystal oscillator of claim 1 wherein the back gate bias control circuit includes a second body resistor connected between a body and a source of the other of the n-type metal oxide semiconductor transistor or the p-type metal oxide semiconductor transistor, and a second controllable current source configured to provide a second current to the second body resistor.

7 . The crystal oscillator of claim 1 further comprising a reference voltage control circuit configured to provide a reference voltage to a source of the p-type metal oxide semiconductor transistor, the reference voltage control circuit configured to further adjust the negative resistance of the inverter by controlling a voltage level of the reference voltage.

8 . The crystal oscillator of claim 7 wherein the reference voltage control circuit sets the reference voltage to a first level during startup and to a second level during steady state operation.

9 . The crystal oscillator of claim 1 wherein a source of the p-type metal oxide semiconductor transistor is connected to a reference voltage, a gate of the p-type metal oxide semiconductor transistor is connected to an input of the inverter, a drain of the p-type metal oxide semiconductor transistor is connected to an output of the inverter, a source of the n-type metal oxide semiconductor transistor is connected to a ground voltage, a gate of the n-type metal oxide semiconductor transistor is connected to the input of the inverter, and a drain of the n-type metal oxide semiconductor transistor is connected to the output of the inverter.

10 . The crystal oscillator of claim 9 further comprising a first feedback resistor connected between the input and the output of the inverter, and a second feedback resistor and a switch connected in series between the input and the output of the inverter.

11 . A method of generating an oscillation signal using a crystal oscillator, the method comprising:

receiving an input oscillation signal from a crystal as an input to an inverter;

inverting the input oscillation using an n-type metal oxide semiconductor transistor and a p-type metal oxide semiconductor transistor of the inverter;

adjusting a negative resistance of the inverter by controlling a body bias of at least one of the n-type metal oxide semiconductor transistor or the p-type metal oxide semiconductor transistor using a back gate bias control circuit;

providing a reference voltage to a source of the p-type metal oxide semiconductor transistor using a reference voltage control circuit; and

further adjusting the negative resistance of the inverter by controlling a voltage level of the reference voltage.

12 . The method of claim 11 wherein adjusting the negative resistance includes controlling a body bias of both the n-type metal oxide semiconductor transistor and the p-type metal oxide semiconductor transistor.

13 . The method of claim 11 wherein the back gate bias control circuit sets the back gate bias to a first level during startup and to a second level during steady state operation.

14 . The method of claim 11 wherein the reference voltage control circuit sets the reference voltage to a first level during startup and to a second level during steady state operation.

15 . A timing system comprising:

a phase locked-loop configured to receive a reference clock signal;

a crystal oscillator including a crystal, an inverter having an input connected to a first terminal of the crystal and an output connected to a second terminal of the crystal, the inverter including an n-type metal oxide semiconductor transistor and a p-type metal oxide semiconductor transistor configured to invert an input oscillation signal from the crystal to generate the reference clock signal, the crystal oscillator further including a back gate bias control circuit configured to adjust a negative resistance of the inverter by controlling a body bias of at least one of the n-type metal oxide semiconductor transistor or the p-type metal oxide semiconductor transistor; and

a reference voltage control circuit configured to provide a reference voltage to a source of the p-type metal oxide semiconductor transistor, the reference voltage control circuit configured to further adjust the negative resistance of the inverter by controlling a voltage level of the reference voltage.

16 . The timing system of claim 15 wherein the back gate bias control circuit sets the back gate bias to a first level during startup of the crystal oscillator and to a second level during steady state operation of the crystal oscillator.

17 . The timing system of claim 15 wherein the back gate bias control circuit includes a first body resistor connected between a body and a source of one of the n-type metal oxide semiconductor transistor or the p-type metal oxide semiconductor transistor, and a first controllable current source configured to provide a first current to the first body resistor.

18 . The method of claim 11 further comprising providing a first current from a first controllable current source to a first body resistor that is connected between a body and a source of one of the n-type metal oxide semiconductor transistor or the p-type metal oxide semiconductor transistor.

19 . The method of claim 18 further comprising providing a second current from a second controllable current source to a second body resistor that is connected between a body and a source of the other of the n-type metal oxide semiconductor transistor or the p-type metal oxide semiconductor transistor.

20 . The method of claim 18 further comprising controlling a first bypass switch connected in parallel with the first body resistor.

Assignments (1)

Continuity (2)

References Cited (34)