Granted Patent B2

US 12,255,584 · App. 18/037,259 · Granted Mar 18, 2025

Inventors: Erlend Strandvik (Trondheim, NO); Hsin-Ta Wu (Trondheim, NO)

Assignee: Nordic Semiconductor ASA

H03B5/364H03B5/06H03L3/00H03L5/00H03B2200/0012H03B2200/0094

Abstract

Claims (45)

1. An electronic device comprising:

an oscillator circuit portion comprising an inverter having an input terminal and an output terminal, said oscillator circuit portion further comprising a crystal oscillator connected between the input and output terminals of the inverter;

an amplitude regulator circuit portion arranged to supply a current to the inverter of the oscillator circuit portion, said amplitude regulator circuit portion being arranged to monitor a voltage at the input terminal of the inverter and to vary the current supplied to said inverter in response to said monitored voltage;

wherein the amplitude regulator circuit portion comprises:

a trimmable resistor arranged such that the voltage at the input terminal of the inverter is set to an operating point when the supply current provided by the amplitude regulator circuit portion is equal to a threshold value, wherein said operating point is at least partly determined by a selected resistance of the trimmable resistor; and

a current monitor arranged to monitor the current supplied to the inverter during operation and to determine therefrom whether the voltage at the input terminal of the inverter is within a predetermined range;

wherein the current monitor comprises a current comparator arranged to determine whether the voltage at the input terminal of the inverter is within the predetermined range.

2. The electronic device as claimed in claim 1 , wherein the operating point is zero.

3. The electronic device as claimed in claim 1 , wherein the operating point is a non-zero value.

4. The electronic device as claimed in claim 3 , wherein the operating point is between approximately 200 mV and 400 mV, optionally between approximately 225 mV and 375 mV, further optionally between approximately 300 mV and 375 mV.

5. The electronic device as claimed in claim 4 , wherein the operating point is approximately 300 mV.

6. The electronic device as claimed in claim 1 , wherein the current comparator is arranged to compare the supply current to a lower bound and an upper bound, where the lower and upper bounds define the predetermined range.

7. The electronic device as claimed in claim 6 , wherein the lower and upper bounds are provided to the comparator as lower and upper reference currents, respectively.

8. The electronic device as claimed in claim 1 , wherein the current monitor comprises a plurality of current comparators each arranged to compare the supply current to a respective threshold value.

9. The electronic device as claimed in claim 8 , wherein the current monitor comprises first and second current comparators, wherein the first current comparator compares the current supplied to the inverter to the lower bound; and wherein the second current comparator compares the current supplied to the inverter to the upper bound.

10. The electronic device as claimed in claim 9 , wherein the lower and upper bounds are provided to the first and second comparators as lower and upper reference currents, respectively.

11. The electronic device as claimed in claim 1 , wherein the amplitude regulator circuit portion comprises first, second, and third PMOS transistors, and first and second NMOS transistors, said amplitude regulator circuit portion being arranged such that:

an input node of the amplitude regulator circuit portion is connected to the input terminal of the inverter, a respective gate terminal of each of the first and second NMOS transistors, and a respective drain terminal of each of the first NMOS transistor and first PMOS transistor;

a drain terminal of the second NMOS transistor is connected to a drain terminal of the second PMOS transistor;

a respective source terminal of each of the first, second, and third PMOS transistors is connected to a positive supply rail;

a respective source terminal of each of the first and second NMOS transistors is connected to a negative supply rail or ground, wherein the source terminal of the second NMOS transistor is connected to the negative supply rail or ground via the trimmable resistor;

a respective gate terminal of each of the first, second, and third PMOS transistors are connected together; and

a drain terminal of the third PMOS transistor is connected to a current input of the inverter of the oscillator circuit portion.

12. The electronic device as claimed in claim 11 , wherein the gate terminal of the second NMOS transistor is connected to the input node of the amplitude regulator circuit portion via a low pass filter wherein the low pass filter comprises a filter resistor and a filter capacitor arranged such that:

a first terminal of the filter resistor is connected to the gate terminal of the first NMOS transistor;

a second terminal of the filter resistor is connected to the gate terminal of the second NMOS transistor and to a first terminal of the filter capacitor; and

a second terminal of the filter capacitor is connected to the negative supply rail or ground.

13. The electronic device as claimed in claim 11 , wherein a decoupling capacitor is connected between the gate terminal of the first NMOS transistor and the negative supply rail or ground.

14. The electronic device as claimed in claim 11 , wherein the gate terminal of the first NMOS transistor is connected to the drain terminals of the first PMOS and first NMOS transistors via a resistor.

15. The electronic device as claimed in claim 11 , wherein the amplitude regulator circuit portion comprises a fourth PMOS transistor arranged such that:

a gate terminal of the fourth PMOS transistor is connected to the gate terminals of the second and third PMOS transistors and to the drain terminal of the second PMOS transistor;

a source terminal of the fourth PMOS transistor is connected to the positive supply rail; and

a drain terminal of the fourth PMOS transistor is connected to the current monitor.

16. An amplitude regulator circuit portion arranged to supply a current to an inverter in an oscillator circuit portion, said amplitude regulator circuit portion being arranged to monitor a voltage at an input terminal of the inverter and to vary the current supplied to said inverter in response to said monitored voltage;

wherein the amplitude regulator circuit portion comprises:

a trimmable resistor arranged such that the voltage at the input terminal of the inverter is set to an operating point when the supply current provided by the amplitude regulator circuit portion is equal to a threshold value, wherein said operating point is at least partly determined by a selected resistance of the trimmable resistor; and

a current monitor arranged to monitor the current supplied to the inverter during operation and to determine therefrom whether the voltage at the input terminal of the inverter is within a predetermined range;

wherein the current monitor comprises a current comparator arranged to determine whether the voltage at the input terminal of the inverter is within the predetermined range.

17. The amplitude regulator circuit portion as claimed in claim 16 , further comprising first, second, and third PMOS transistors, and first and second NMOS transistors, said amplitude regulator circuit portion being arranged such that:

an input node of the amplitude regulator circuit portion is connected to the input terminal of the inverter, a respective gate terminal of each of the first and second NMOS transistors, and a respective drain terminal of each of the first NMOS transistor and first PMOS transistor;

a drain terminal of the second NMOS transistor is connected to a drain terminal of the second PMOS transistor;

a respective source terminal of each of the first, second, and third PMOS transistors is connected to a positive supply rail;

a respective source terminal of each of the first and second NMOS transistors is connected to a negative supply rail or ground, wherein the source terminal of the second NMOS transistor is connected to the negative supply rail or ground via the trimmable resistor;

a respective gate terminal of each of the first, second, and third PMOS transistors are connected together; and

a drain terminal of the third PMOS transistor is arranged for connection to a current input of the inverter of the oscillator circuit portion.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (26)