Low power crystal oscillator

1. A circuit, comprising:

a first transistor;

a current source for driving a drain of the first transistor with a bias current;

a first decoupling capacitor for isolating a direct current (DC) drain voltage for the first transistor from a DC gate voltage for the first transistor, wherein a gate of the first transistor is configured to be biased by an AC input voltage from a crystal through the first decoupling capacitor;

a first inverter configured to invert a voltage at a terminal of the first decoupling capacitor;

a second inverter configured to invert an output signal from the first inverter to provide an output voltage for the circuit;

an operational amplifier configured to further bias the gate of the first transistor responsive to a comparison between the DC drain voltage and a reference voltage to regulate the DC drain voltage to equal the reference voltage; and

a reference inverter including a reference PMOS transistor having a source connected to a power supply node for supplying a power supply voltage, a reference NMOS transistor having a source connected to ground and having a drain connected to a drain of the reference PMOS transistor, and a reference resistor connected between the drain of the reference NMOS transistor and a reference node for supplying the reference voltage, wherein the reference node is connected to a gate of the reference PMOS transistor and to a gate of the reference NMOS transistor, and wherein the reference inverter is matched to the first inverter and to the second inverter.

2. The circuit of claim 1 , further comprising:

a voltage divider having a first resistor having a first terminal connected to the drain of the first transistor and having a second terminal connected to a first terminal of a second resistor, wherein the operational amplifier has a first input connected to the second terminal of the first resistor and has a second input connected to reference voltage node for carrying the reference voltage.

3. The circuit of claim 2 , wherein the first input is a positive input for the operational amplifier, and wherein the second input is a negative input for the operational amplifier.

4. The circuit of claim 2 , further comprising a biasing resistor coupled between an output of the operational amplifier and the gate of the first transistor.

5. The circuit of claim 4 , further comprising a feedback capacitor coupled between the output of the operational amplifier and the ground.

6. The circuit of claim 2 , wherein a second terminal of the voltage divider is coupled to a terminal of the first decoupling capacitor.

7. The circuit of claim 6 , wherein the first transistor is an NMOS transistor having a source connected to the ground, and wherein the current source comprises a PMOS current source transistor having a source connected to the power supply node for supplying the power supply voltage and a drain connected to the drain of the NMOS transistor.

8. The circuit of 7 , further comprising a second decoupling capacitor coupled between the terminal of the first decoupling capacitor and a gate of the PMOS current source transistor.

9. The circuit of claim 7 , further comprising:

a diode-connected PMOS transistor having a gate coupled to a gate of the PMOS current source transistor; and

a current source coupled between a drain of the diode-connected PMOS transistor and the ground.

10. The circuit of claim 9 , further comprising a bias resistor configured to couple the gate of the diode-connected PMOS transistor to the gate of the PMOS current source transistor.

11. The circuit of claim 1 , wherein the circuit is integrated within an integrated circuit in a circuit package, the circuit package further comprising the crystal having a first terminal connected to the drain of the first transistor and having a second terminal connected to the terminal of the first decoupling capacitor.

12. A method of oscillating an output signal, comprising:

biasing a direct current (DC) gate voltage of a gate of a first transistor in a Pierce oscillator by driving a drain of the first transistor with a current from a current source;

isolating the gate from the drain through a first decoupling capacitor;

generating a reference voltage using a reference inverter such that the reference voltage equals a threshold voltage of the reference inverter;

amplifying a difference between the reference voltage and a DC drain voltage for the drain to bias an alternating current (AC) gate voltage for the gate to cause the DC drain voltage to equal the reference voltage;

driving the gate of the first transistor with an oscillating voltage from a crystal through the first decoupling capacitor;

inverting the oscillating voltage in a first inverter to form an inverter output signal; and

inverting the inverter output signal in a second inverter to form an oscillating output signal, wherein the reference inverter is matched to the first inverter and to the second inverter.

13. The method of claim 12 , further comprising:

generating the current from the current source in a second transistor; and

coupling the oscillating voltage from the crystal through a second decoupling capacitor to a gate of the second transistor.