IP Library Granted Patent US 11,476,928
Granted Patent B2
US 11,476,928 · App. 16/921,993 · Granted Oct 18, 2022

TDMA networking using commodity NIC/switch

Inventors: Dotan David Levi (Kiryat Motzkin, IL); Avi Urman (Yokneam Illit, IL); Lior Narkis (Petah-Tikva, IL); Liron Mula (Ramat Gan, IL); Paraskevas Bakopoulos (Ilion, GR); Ariel Almog (Kohav Yahir, IL); Roee Moyal (Yokneam Illit, IL); Gal Yefet (Haifa, IL)
Assignee: MELLANOX TECHNOLOGIES, LTD.
H04B7/2646H04L49/351H04L49/90H04W72/0446H04W74/08
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,476,928
App. No.
16/921,993
Granted
Oct 18, 2022
Kind
B2
Abstract

A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound packets, which are received from the communication network, depending on the timeslots.

Claims (39)

1. A network element, comprising:

one or more network ports configured to communicate with a communication network;

network time circuitry, configured to track a network time defined in the communication network; and

packet processing circuitry, configured to:

generate a series of evenly spaced entries including time stamps from the network time circuitry;

receive indications of packets to be transmitted along with a definition of timeslots assigned to transmission of the indicated packets; and

send outbound packets to the communication network in accordance with the received indications and assigned timeslots, at times responsive to the entries of the generated series.

2. The network element according to claim 1 , wherein the timeslots comprise a plurality of timeslots that are assigned to the network element in a periodic time schedule that is synchronized to the network time.

3. The network element according to claim 1 , wherein the packet processing circuitry is configured to send the outbound packets only during the assigned timeslots.

4. The network element according to claim 1 , wherein the packet processing circuitry is configured to generate the series of evenly spaced entries by generating a series of evenly spaced dummy packets, and generating completion queue entries including time stamps from the network time circuitry, responsive to the dummy packets.

5. The network element according to claim 4 , wherein the dummy packets do not egress the network element.

6. The network element according to claim 4 , wherein the series of evenly spaced dummy packets comprises fixed duration dummy packets.

7. The network element according to claim 1 , wherein the network ports are configured to send the outbound packets to a wireless network operating in Time-Division Multiple Access (TDMA).

8. The network element according to claim 1 , wherein the network ports are configured to send the outbound packets to an optical switching network operating in Time-Division Multiple Access (TDMA).

9. The network element according to claim 1 , wherein, in addition to sending the outbound packets depending on the timeslots, the packet processing circuitry is configured to send additional packets to the communication network independently of the timeslots.

10. The network element according to claim 1 , wherein the outbound packets comprise Ethernet packets or Infiniband packets.

11. The network element according to claim 1 , wherein the packet processing circuitry receives the indications of the packets to be transmitted in queues, which further include wait commands which indicate the assigned timeslots.

12. The network element according to claim 1 , further comprising a time-based circuitry that blocks any packet that the egress circuitry may attempt to send to the network outside the allocated timeslot.

13. A network element, comprising:

one or more network ports configured to communicate with a communication network;

network time circuitry, configured to track a network time defined in the communication network; and

packet processing circuitry, configured to:

receive a definition of one or more timeslots that are synchronized to the network time; and

process inbound packets, which are received from the communication network, depending on the respective timeslots in which the inbound packets were received.

14. The network element according to claim 13 , wherein the packet processing circuitry is configured to process an inbound packet only if an arrival time of the inbound packet is during the one or more timeslots.

15. A network element, comprising:

one or more network ports configured to communicate with a communication network;

network time circuitry, configured to track a network time defined in the communication network; and

packet processing circuitry, configured to:

queue outbound packets in one or more queues;

assign credits to the queues depending on the network time; and

transmit the outbound packets to the communication network in accordance with the assigned credits.

16. A network element, comprising:

one or more network ports configured to communicate with a communication network;

network time circuitry, configured to track a network time defined in the communication network; and

packet processing circuitry, configured to:

receive inbound packets from the communication network;

determine times-of-arrival of the inbound packets, in accordance with the network time; and

distribute the inbound packets to multiple queues based on the times-of-arrival.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2020
From: YEFET, GAL
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 054331/0613 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2020
From: LEVI, DOTAN DAVID; URMAN, AVI; NARKIS, LIOR; MULA, LIRON; BAKOPOULOS, PARASKEVAS; ALMOG, ARIEL; MOYAL, ROEE
To: MELLANOX TECHNOLOGIES, LTD.
Reel/Frame 053133/0676 →
Priority Claims (1)
GR 20200100141 · Mar 18, 2020 · national
Continuity (1)
Related Publication 20210297151A1 · Sep 23, 2021
Cited By (14)
US 12,216,489 US 12,255,734 US 12,289,388 US 12,289,389 US 12,294,469 US 12,308,952 US 12,375,199 US 12,524,038 US 12,549,487 US 12,615,130 US 12,634,240 US 12,645,251 US 12,669,843 US 12,712,703