Clock data recovery convergence in modulated partial response systems
A clock data recovery circuit detects illegal decisions for received data, accumulates a phase gradient for the data, determines a number of the illegal decisions in a configured window for receiving the data, and if the number of the illegal decisions exceeds a pre-defend number in the window, applies a sum of the accumulated phase gradient and a phase increment having a sign of the accumulated phase gradient to a clock circuit for the data receiver.
1. A clock recovery circuit comprising:
a detector configured to receive data and detect illegal decisions;
a phase detector to form an accumulated phase gradient; and
logic to:
determine a number of occurrence of the illegal decisions;
on condition that the number of illegal decisions exceeds a pre-defend number over a pre-defined time period, add to the accumulated phase gradient a phase increment having a sign of the accumulated phase gradient; and
apply the phase increment to a clock circuit.
2. The clock recovery circuit of claim 1 , further comprising:
a digital loop filter to receive the phase increment and apply it to the clock circuit.
3. The clock recovery circuit of claim 2 , wherein the phase increment is applied to a timing estimate at one of an input an an output of the loop filter.
4. The clock recovery circuit of claim 2 , wherein the phase increment is applied at an intermediate node of the loop filter.
5. The clock recovery circuit of claim 1 , wherein the clock circuit is a phase interpolator.
6. The clock recovery circuit of claim 1 , wherein the clock circuit is a digital controlled oscillator.
7. The clock recovery circuit of claim 1 , wherein the clock recovery circuit is coupled to a first order partial response (PR 1 ) system.
8. The clock recovery circuit of claim 1 , wherein the clock recovery circuit is coupled to a second order partial response (PR 2 ) system.
9. The clock recovery circuit of claim 1 , wherein the phase increment is a programmable value.
10. A receiver for four-level pulse-amplitude modulated (PAM-4) signals, the receiver comprising:
logic to receive PAM-4 encoded data and detect illegal decisions;
a clocking element; and
logic to:
determine a number of occurrence of the illegal decisions;
on condition that the number of illegal decisions exceeds a pre-defend number, inject a phase increment into the clocking element, the phase increment having a sign of an accumulated phase gradient for the PAM-4 encoded data; and
apply the phase increment to the clock element.
11. The receiver of claim 10 , further comprising:
a digital loop filter to receive the phase increment and apply it to the clock element.
12. The receiver of claim 11 , wherein the phase increment is applied to a timing estimate at one of an input an output of the loop filter.
13. The receiver of claim 11 , wherein the phase increment is applied at an intermediate node of the loop filter.
14. The receiver of claim 10 , wherein the clock element is a phase interpolator.
15. The receiver of claim 10 , wherein the clock element is a digital controlled oscillator.
16. The receiver of claim 10 , further comprising a duobinary partial response system.
17. The receiver of claim 10 , further comprising a second-order loop filter.
18. The receiver of claim 10 , wherein the phase increment is a programmable value.
19. A method comprising:
detecting illegal decisions in a data receiver;
accumulating a phase gradient for the data;
determining a number of occurrence of the illegal decisions;
on condition that the number of illegal decisions exceeds a pre-defend number over a pre-defined time period, adding to the accumulated phase gradient a phase increment having a sign of the accumulated phase gradient; and
applying the phase increment to a clock circuit.
20. The method of claim 19 , wherein the receiver comprises a first order partial response (PR 1 ) system.
21. The method of claim 19 , wherein the receiver comprises a second order partial response (PR 2 ) system.