Imaging device and imaging system
In an imaging device according to the present disclosure, during a period in which a signal from an amplifier transistor is output from a pixel via a select transistor, the gate voltage of the capacitance addition transistor changes frons the first voltage VH to the second voltage VL, and the amount of voltage change per time until the gate voltage changes from the first voltage VH to the second voltage VL is smaller than the amount of voltage change per unit time until the gate voltage changes from the second voltage VL to the first voltage VH.
1. An imaging device comprising:
a pixel including a photoelectric converter; an amplifier transistor having an input node that holds charge from the photoelectric converter and configured to output a signal based on the charge of the input node; a select transistor configured to output the signal output from the amplifier transistor to a readout circuit fifer ding out the signal; a reset transistor configured to set a potential of the input node to a prescribed reset potential; and a capacitance addition transistor connected to the input node and configured to switch the capacitance value of the input node; and
a drive circuit configured to turn on the capacitance addition transistor by setting a gate voltage of the capacitance addition transistor to a fast voltage, and turn off the capacitance addition transistor by setting the gate voltage of the capacitance addition transistor to a second voltage,
wherein the gate voltage is changed from the first voltage to the second voltage during a period when the signal from the amplifier transistor is output from the pixel via the select transistor, and
wherein a voltage change amount per unit time when the gate voltage changes from the first voltage to the second voltage is smaller than a voltage change amount per unit time when the gate voltage changes from the second voltage to the first voltage.
2. The imaging device according to claim 1 , wherein the gate voltage changes from the first voltage to the second voltage during a period in which the reset transistor is in an on-state.
3. The imaging device according to claim 1 , wherein a first main node of the capacitance addition transistor is connected to the input node, and a second main node of the capacitance addition transistor is connected to a capacitor unit.
4. The imaging device according to claim 1 , wherein the capacitance addition transistor is provided in an electrical path between the input node and the reset transistor.
5. The imaging device according claim 4 , wherein a first main node of the capacitance addition transistor is connected to the input node, and a second main node of the capacitance addition transistor is connected to one main node of the reset transistor.
6. The imaging device according to claim 5 , wherein the readout circuit reads out the signal when the capacitance addition transistor is in an off-state and the reset transistor is in an on-state.
7. The imaging device according to claim 5 , wherein the readout circuit reads out the signal when the capacitance addition transistor is in aft on-state and the reset transistor is in an off-state.
8. The imaging device according to claim 4 ,
wherein the capacitance addition transistor includes a first capacitance addition transistor and a second capacitance addition transistor,
wherein a first main node of the first capacitance addition transistor is connected to the input node, and
wherein a first main node of the second capacitance addition transistor is connected to a second main node of the first capacitance addition transistor, and a second main node of the second capacitance addition transistor is connected to one main node of the reset transistor.
9. The imaging device according to claim 8 , wherein the readout circuit is configured to selectively perform one of
a first operation mode in which the readout circuit reads out the signal when the first capacitance addition transistor and the second capacitance addition transistor are in an on-state,
a second operation mode in which the readout circuit reads out the signal when the first capacitance addition transistor is in an on-state and the second capacitance addition transistor is in an off-state, and
a third operation mode in which the readout circuit reads out the signal when the first capacitance addition transistor is in an off-state and the second capacitance addition transistor is in an on-state.
10. The imaging device according to claim 9 , wherein the reset transistor is in an off-state in the first operation mode.
11. The imaging device according to claim 9 , wherein the reset transistor is in an on-state in the second operation mode and the third operation mode.
12. The imaging device according to claim 8 , wherein a gate of the second capacitance addition transistor is connected to a first voltage line supplying the first voltage.
13. The imaging device according to claim 1 ,
wherein the drive circuit drives the gate voltage with a prescribed drive current, and
wherein the drive current for changing the gate voltage from the first voltage to the second voltage is smaller than the drive current for changing the into voltage from the second voltage to the first voltage.
14. The imaging device according to claim 13 , wherein the drive circuit includes
a first transistor which is in an on-state when the gate voltage is changed from the first voltage to the second voltage; and
a current source which is provided in an electrical path between a first main node of the first transistor and a second voltage line supplying the second voltage and configured to define the drive current.
15. The imaging device according to claim 14 , further comprising a second transistor which is in an on-state when the gate voltage is changed from the second voltage to the first voltage,
wherein the first voltage is supplied to a second main node of the second transistor.
16. The imaging device according to claim 15 , wherein driving circuit is configured to set the gate voltage to a voltage intermediate between the first voltage and the second voltage during a period in which the photoelectric converter accumulates charge.
17. The imaging device according to claim 16 , herein the drive circuit further includes a second switch circuit configured to selectively supply to the second main node of the second transistor one of the first voltage and a third voltage intermediate between the first voltage and the second voltage.
18. The imaging device according to claim 17 , herein the drive circuit further includes a first switch circuit configured to selectively supply to the first main node of the first transistor one of the second voltage and a fourth age intermediate between the first voltage and the second voltage.
19. An imaging system comprising:
imaging device according to claim 1 ; and
a signal processing unit configured to process an image signal output from the imaging device.
20. The imaging system according to claim 19 ,
wherein the pixel includes a plurality of photoelectric converters, and
wherein the signal processing unit is configured to process the image signals generated by the plurality of photoelectric converters, respectively, and acquire a distance information from the imaging device to an object.