IP Library › Granted Patent US 11,477,405
Granted Patent B2
US 11,477,405 · App. 17/193,434 · Granted Oct 18, 2022

Solid-state image sensor

Inventors: Takeo Ushinaga (Sakai, JP); Yoshinao Morikawa (Sakai, JP)
Assignee: SHARP KABUSHIKI KAISHA
H04N5/37455H03M1/0872H03M1/56H04N5/378
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Quick Facts
Patent No.
US 11,477,405
App. No.
17/193,434
Granted
Oct 18, 2022
Kind
B2
Abstract

An AD conversion circuit provided in a solid-state image sensor includes a counter circuit that performs count processing and a first latch circuit that holds at least one of a discrimination result of a first comparison circuit and a first output result of the counter circuit.

Claims (35)

1. A solid-state image sensor comprising:

a pixel unit in which a plurality of unit pixels for photoelectric conversion of incident light are arranged;

an AD conversion circuit that performs AD conversion on a potential of an analog signal read from a pixel signal line connected to the plurality of unit pixels; and

a discrimination circuit that discriminates whether or not a reset potential at the potential of the analog signal is higher than a predetermined first reference potential,

wherein the AD conversion circuit includes

a counter circuit that performs count processing and

a first latch circuit that holds both a discrimination result of the discrimination circuit and a first output result output from the counter circuit.

2. A solid-state image sensor comprising:

a pixel unit in which a plurality of unit pixels for photoelectric conversion of incident light are arranged;

an AD conversion circuit that performs AD conversion on a potential of an analog signal read from a pixel signal line connected to the plurality of unit pixels; and

a discrimination circuit that discriminates whether or not a reset potential at the potential of the analog signal is higher than a predetermined first reference potential,

wherein the AD conversion circuit includes

a counter circuit that performs count processing,

a first latch circuit that holds at least a discrimination result of the discrimination circuit among the discrimination result of the discrimination circuit and a first output result output from the counter circuit, and

a comparison circuit that compares the potential of the analog signal with a second reference potential which is a potential of a ramp waveform that changes with time,

the AD conversion circuit performs AD conversion on the potential of the analog signal during a first count period and a second count period after the first count period,

the counter circuit,

sets an initial value of first count processing performed during the first count period as a negative value,

stops the first count processing with a change in an output signal output from the comparison circuit as a trigger,

inverts all bits of a first count value when the first count processing is stopped before starting second count processing performed during the second count period, and

uses a value obtained by inverting all the bits of the first count value as an initial value of the second count processing performed during the second count period,

the first latch circuit holds a most significant bit of the first count value output from the counter circuit, and

the AD conversion circuit further includes a second latch circuit that holds all bits of a second count value output from the counter circuit when the second count processing is stopped.

3. The solid-state image sensor according to claim 2 , further comprising:

a post-stage processing logic circuit to which the discrimination result and the first output result that are output from the first latch circuit and a second output result that is output from the second latch circuit are respectively input, wherein

the post-stage processing logic circuit outputs any of the second output result output from the second latch circuit or a replacement result that is obtained by replacing the second output result with a full code in the post-stage processing logic circuit, in accordance with the discrimination result output from the first latch circuit.

4. The solid-state image sensor according to claim 1 ,

wherein the discrimination circuit is a comparator circuit that compares the reset potential with the predetermined first reference potential.

5. A solid-state image sensor comprising:

a pixel unit in which a plurality of unit pixels for photoelectric conversion of incident light are arranged;

an AD conversion circuit that performs AD conversion on (i) a potential corresponding to a difference between a signal potential and a reset potential at a potential of an analog signal read from a pixel signal line connected to the plurality of unit pixels and (ii) a predetermined reference potential; and

a discrimination circuit that discriminates whether or not the reset potential at the potential of the analog signal is higher than a predetermined first reference potential,

wherein the AD conversion circuit includes

a counter circuit that performs count processing and

a first latch circuit that holds a discrimination result of the discrimination circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2021
From: USHINAGA, TAKEO; MORIKAWA, YOSHINAO
To: SHARP KABUSHIKI KAISHA
Reel/Frame 055508/0730 →
Continuity (2)
Provisional Application 63003558 · Apr 1, 2020
Related Publication 20210314518A1 · Oct 7, 2021