IP Library › Granted Patent US 11,477,406
Granted Patent B2
US 11,477,406 · App. 16/961,049 · Granted Oct 18, 2022

Imaging device and electronic apparatus for effective pixel signal reading

Inventors: Tatsuji Ashitani (Kanagawa, JP); Yukiyasu Tatsuzawa (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H04N5/37457H01L27/14603H01L27/14612H01L27/14636H01L27/14641H01L27/14643H04N5/347
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Quick Facts
Patent No.
US 11,477,406
App. No.
16/961,049
Granted
Oct 18, 2022
Kind
B2
Abstract

An imaging device according to the present disclosure includes a plurality of pixel units each including a first pixel unit and a second pixel unit and a vertical signal line, in which each of the first pixel unit and the second pixel unit includes an amplification transistor, a selection transistor connected between the amplification transistor and the vertical signal line, and a connection unit that selectively connects between a common connection node of the amplification transistor and the selection transistor of the first pixel unit and a common connection node of the amplification transistor and the selection transistor of the second pixel unit.

Claims (52)

1. An imaging device, comprising:

a plurality of pixel units, wherein

each of the plurality of pixel units includes a first pixel unit and a second pixel unit,

each of the first pixel unit and the second pixel unit includes a first pixel group and a second pixel group, and

each of the first pixel group and the second pixel group includes a plurality of pixels; and

a vertical signal line, wherein each of the first pixel unit and the second pixel unit includes:

a plurality of transfer transistors, wherein

each of the plurality of transfer transistors is in a corresponding pixel of the plurality of pixels, and

the plurality of transfer transistors is in a square arrangement in each of the first pixel group and the second pixel group;

an amplification transistor;

a selection transistor connected between the amplification transistor and the vertical signal line; and

a connection transistor configured to selectively connect between a common connection node of the amplification transistor and the selection transistor of the first pixel unit and a common connection node of the amplification transistor and the selection transistor of the second pixel unit, wherein the connection transistor is adjacent to the square arrangement of the plurality of transfer transistors corresponding to the first pixel group.

2. The imaging device according to claim 1 , wherein

the connection transistor is further configured to selectively connect the second pixel unit to the first pixel unit,

the second pixel unit comprises a single pixel unit or a plurality of second pixel units,

each of the first pixel unit and the second pixel unit corresponds to a unit group, and

each of the plurality of pixel units corresponds to a unit of the unit group.

3. The imaging device according to claim 2 , wherein

a signal of each pixel in the first pixel unit and the second pixel unit is output through the vertical signal line that is associated with the unit group, and

the vertical signal line associated with the unit group is a single vertical signal line.

4. The imaging device according to claim 3 , wherein

each of the first pixel unit and the second pixel unit further includes a reset transistor,

each of the reset transistor, the amplification transistor, and the selection transistor is shared by the first pixel group and the second pixel group,

the reset transistor is configured to reset a floating diffusion that converts a charge photoelectrically converted by each pixel in a corresponding pixel unit into a pixel signal,

the amplification transistor is configured to read the pixel signal converted by the floating diffusion, and

the selection transistor is configured to selectively output the pixel signal read by the amplification transistor to the single vertical signal line associated with the unit group.

5. The imaging device according to claim 4 , wherein one end of the connection transistor is connected to the common connection node of the amplification transistor and the selection transistor in each pixel unit of the plurality of pixel units.

6. The imaging device according to claim 5 , wherein

each of the first pixel group and the second pixel group includes four pixels that are in two rows and two columns,

the plurality of transfer transistors corresponding to the four pixels in each of the first pixel group and the second pixel group is in the square arrangement,

two transistors among the reset transistor, the amplification transistor, and the selection transistor are between the first pixel group and the second pixel group in correspondence with the plurality of transfer transistors in the square arrangement,

a third transistor among the reset transistor, the amplification transistor, and the selection transistor adjacent to the square arrangement of the plurality of transfer transistors corresponding to the first pixel group,

the third transistor is other than the two transistors, and

the third transistor is next to the connection transistor.

7. The imaging device according to claim 1 , wherein

the connection transistor is further configured to realize binning reading, and

a signal of a pixel is read based on an assumption that the plurality of pixels is a single pixel.

8. The imaging device according to claim 1 , wherein the connection transistor is further configured to realize cutout reading to read a signal of a pixel in a specific region.

9. The imaging device according to claim 1 , wherein the connection transistor is further configured to realize thinning reading to read a signal of a pixel in a specific pixel row.

10. An electronic apparatus, comprising:

an imaging device that includes:

a plurality of pixel units, wherein

each of the plurality of pixel units includes a first pixel unit and a second pixel unit,

each of the first pixel unit and the second pixel unit includes a first pixel group and a second pixel group, and

each of the first pixel group and the second pixel group includes a plurality of pixels; and

a vertical signal line, wherein each of the first pixel unit and the second pixel unit includes:

a plurality of transfer transistors, wherein

each of the plurality of transfer transistors is in a corresponding pixel of the plurality of pixels, and

the plurality of transfer transistors is in a square arrangement in each of the first pixel group and the second pixel group;

an amplification transistor;

a selection transistor connected between the amplification transistor and the vertical signal line; and

a connection transistor configured to selectively connect between a common connection node of the amplification transistor and the selection transistor of the first pixel unit and a common connection node of the amplification transistor and the selection transistor of the second pixel unit, wherein the connection transistor is adjacent to the square arrangement of the plurality of transfer transistors corresponding to the first pixel group.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2021
From: ASHITANI, TATSUJI; TATSUZAWA, YUKIYASU
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 055938/0273 →
Priority Claims (1)
JP JP2018-009367 · Jan 24, 2018 · national
Continuity (1)
Related Publication 20210067726A1 · Mar 4, 2021