IP Library › Granted Patent US 11,480,989
Granted Patent B2
US 11,480,989 · App. 17/322,175 · Granted Oct 25, 2022

High accuracy zener based voltage reference circuit

Inventors: Hongwei Liu (Toulouse, FR); Yuan Gao (Cugnaux, FR); Estelle Huynh (Villeneuve-Tolosane, FR)
Assignee: NXP USA, Inc.
G05F3/185
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Quick Facts
Patent No.
US 11,480,989
App. No.
17/322,175
Granted
Oct 25, 2022
Kind
B2
Abstract

A voltage reference circuit is disclosed comprising: a supply terminal; a ground terminal; a first current source and a Zener diode connected in series between the supply and ground terminals and having a first node therebetween and configured to supply a Zener voltage at the first node; an output node configured to provide a voltage reference; and a CTAT, circuit connected between the first node and the output node; wherein the CTAT circuit comprises: two bipolar transistors, having their respective emitters connected at a second node, and configured to, in operation, have equal collector-emitter currents, the base of the first bipolar transistor being connected to the first node, the base of the second bipolar transistor being connected to a centre node of a first voltage divider; and wherein the first voltage divider is connected between the emitter of the second bipolar transistor and the output node.

Claims (42)

1. A voltage reference circuit comprising:

a supply terminal configured to be connected to a supply voltage;

a ground terminal configured to be connected to a ground voltage;

a first current source and a Zener diode connected in series between the supply terminal and the ground terminal and having a first node therebetween and configured to supply a Zener voltage at the first node;

an output node configured to provide a voltage reference; and

a complementary to absolute temperature, CTAT, circuit connected between the first node and the output node;

wherein the CTAT circuit comprises:

a first bipolar transistor and a second bipolar transistor, each having a base, a collector and an emitter, having their respective emitters connected at a second node, and configured to, in operation, have equal collector-emitter currents,

wherein the base of the first bipolar transistor is connected to the first node and the base of the second bipolar transistor is connected to a centre node of a first voltage divider, and

wherein the first voltage divider consists of a first resistance connected between the output node and the centre node and a second resistance connected between the centre node and the emitter of the second bipolar transistor.

2. A voltage reference circuit as claimed in claim 1 , wherein the CTAT circuit further comprises a second current source, connected between the collector of the first bipolar transistor and the supply node, and configured to provide a bias current to the first bipolar transistor.

3. A voltage reference circuit as claimed in claim 1 , wherein the CTAT circuit further comprises a FET having main terminals connected between the collector of the second bipolar transistor and the supply node, and a control terminal connected to the collector of the first bipolar transistor, and configured to match the collector-emitter currents through the first and second bipolar transistors.

4. A voltage reference circuit as claimed in claim 1 , wherein the CTAT circuit further comprises a third current source, connected between the emitters of the first and second bipolar transistors, and the ground terminal.

5. A voltage reference circuit as claimed in claim 1 , wherein the third current source is configured to sink a current equal to twice that supplied by the second current source plus a current through the second resistor.

6. A voltage reference circuit as claimed in claim 1 , wherein the voltage reference is provided directly at the output node.

7. A voltage reference circuit as claimed in claim 1 , further comprising a second voltage divider comprising two resistors connected between the output node and ground and having a centre node therebetween, wherein the voltage reference is at the centre node of the second voltage divider.

8. A voltage reference circuit as claimed in claim 1 , wherein the first bipolar transistor and the second bipolar transistor are each NPN transistors.

9. A voltage reference circuit as claimed in claim 1 , wherein the first bipolar transistor and second bipolar transistor are matched transistors.

10. A voltage reference circuit as claimed in claim 1 , wherein the current through the first voltage divider is less than 100 nA.

11. A voltage reference circuit as claimed in claim 3 , configured to operate with a minimum supply voltage which is the sum of the Zener voltage and a gate-source voltage across the FET.

12. A voltage reference circuit as claimed in claim 1 , configured to operate with a supply voltage between 6 V and 7 V.

13. A voltage reference circuit as claimed in claim 1 , wherein the second current source and the third current source are each configured to have a zero temperature coefficient, OTC.

14. A voltage reference circuit as claimed in claim 4 , wherein the third current source is configured to sink a current consisting of a proportional to absolute temperature, PTAT, component and a CTAT component, wherein the CTAT component is a scaled version of a current through the second resistor.

15. A voltage reference circuit as claimed in claim 1 , wherein the CTAT circuit further comprises a third current source, connected between the emitters of the first and second bipolar transistors, and the ground terminal.

16. A voltage reference circuit comprising:

a supply terminal configured to be connected to a supply voltage;

a ground terminal configured to be connected to a ground voltage;

a first current source and a Zener diode connected in series between the supply terminal and the ground terminal and having a first node therebetween and configured to supply a Zener voltage;

an output node configured to provide the voltage reference; and

a complementary to absolute temperature, CTAT, circuit connected between the first node and the output node;

wherein the CTAT circuit comprises a first bipolar transistor and a second bipolar transistor having matched emitter currents wherein the first bipolar transistor is configured to receive the Zener voltage at its base, and the voltage reference is derived from a voltage at the base of the second bipolar transistor.

17. The voltage reference circuit of claim 16 , wherein

the first bipolar transistor and the second bipolar transistor, each having a base and a collector and an emitter, with their respective emitters connected at a second node, wherein

the collector of the first transistor is connected to the supply terminal by a second current source,

the collector of the second transistor is connected to the output node, and to the supply terminal through a FET,

and the base of the first bipolar transistor is connected to the first node;

a voltage divider connected in parallel with the second bipolar transistor and having a centre node connected to the base of the second transistor, a lower terminal connected to the second node, and

an upper terminal connected to the output node; and

a third current source connected between the ground terminal and the second node.

18. The voltage reference circuit of claim 17 , further comprising a second voltage divider comprising two resistors connected between the output node and ground and having a centre node therebetween, wherein the voltage reference is at the centre node of the second voltage divider.

19. The voltage reference circuit of claim 18 , wherein the CTAT circuit further comprises a second current source, connected between the collector of the first bipolar transistor and the supply node, and configured to provide a bias current to the first bipolar transistor.

20. The voltage reference circuit of claim 18 , wherein the CTAT circuit further comprises a third current source, connected between the emitters of the first and second bipolar transistors, and the ground terminal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2021
From: LIU, HONGWEI; GAO, YUAN; HUYNH, ESTELLE
To: NXP USA, INC.
Reel/Frame 056395/0610 →
Priority Claims (1)
EP 20305656 · Jun 16, 2020 · regional
Continuity (1)
Related Publication 20210389791A1 · Dec 16, 2021
Cited By (1)
US 12,625,511