IP Library › Granted Patent US 11,481,218
Granted Patent B2
US 11,481,218 · App. 16/633,071 · Granted Oct 25, 2022

System and method enabling one-hot neural networks on a machine learning compute platform

Inventors: Jianguo Li (Beijing, CN); Yurong Chen (Beijing, CN)
Assignee: Intel Corporation
G06F9/30196G06F9/3016G06F9/30032G06F9/30036G06N3/0445G06N3/0454G06N3/063
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Quick Facts
Patent No.
US 11,481,218
App. No.
16/633,071
Granted
Oct 25, 2022
Kind
B2
Abstract

One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising instruction decode logic to decode a single instruction including multiple operands into a single decoded instruction, the multiple operands including a first operand and a second operand, the first operand including vector of one-hot coded weights and the second operand including a vector of input data; and a general-purpose graphics compute unit including a first logic unit, the general-purpose graphics compute unit to execute the single decoded instruction, wherein to execute the single decoded instruction includes to perform multiple operations on the first set of operands and the second set of operands.

Claims (28)

1. A compute apparatus to perform machine learning operations, the compute apparatus comprising:

instruction decode logic to decode a single instruction including multiple operands into a single decoded instruction, the multiple operands including a first operand and a second operand, the first operand including a vector of one-hot coded weights and the second operand including a vector of input data, the vector of input data including integer input activation data for a layer of a neural network; and

a general-purpose graphics compute unit including a first logic unit, the general-purpose graphics compute unit to execute the single decoded instruction, wherein to execute the single decoded instruction includes to perform multiple operations on the first operand and the second operand.

2. The compute apparatus as in claim 1 , each one-hot coded weight in the vector of one-hot coded weights including a sign bit and a power value.

3. The compute apparatus as in claim 2 , the multiple operations including multiple multiply operations.

4. The compute apparatus as in claim 3 , the multiple multiply operations implemented via vector shift logic.

5. The compute apparatus as in claim 4 , the vector shift logic to shift each element in the vector of input data by a power value of a corresponding one-hot coded weight.

6. The compute apparatus as in claim 5 , the vector shift logic including right-shift logic.

7. The compute apparatus as in claim 6 , the vector shift logic to right-shift each element in the vector of input data by a power value of a corresponding one-hot coded weight.

8. A data processing system comprising:

a memory device; and

a general-purpose graphics processing unit coupled with the memory device, the general-purpose graphics processing unit comprising a decode unit to decode a single instruction including multiple operands into a single decoded instruction, the multiple operands including a first operand and a second operand, the first operand including a vector of one-hot coded weights and the second operand including a vector of input data, the vector of input data including integer input activation data for a layer of a neural network, and a general-purpose graphics compute unit including a first logic unit, the general-purpose graphics compute unit to execute the single decoded instruction, wherein to execute the single decoded instruction includes to perform multiple operations on the first operand and the second operand.

9. The data processing system as in claim 8 , each one-hot coded weight in the vector of one-hot coded weights including a sign bit and a power value.

10. The data processing system as in claim 9 , the multiple operations including multiple multiply operations.

11. The data processing system as in claim 10 , the multiple multiply operations implemented via vector shift logic.

12. The data processing system as in claim 11 , the vector shift logic to shift each element in the vector of input data by a power value of a corresponding one-hot coded weight.

13. The data processing system as in claim 8 , wherein to perform the multiple operations includes to decode the one-hot coded weights of the vector of one-hot coded weights via the first logic unit and perform the multiple operations on the decoded one-hot coded weights and the integer input activation data.

14. The compute apparatus as in claim 1 , wherein to perform the multiple operations includes to decode the one-hot coded weights of the vector of one-hot coded weights via the first logic unit and perform the multiple operations on the decoded one-hot coded weights and the integer input activation data.

15. A method comprising:

decoding, via a general-purpose graphics processing unit, a single instruction including multiple operands into a single decoded instruction, the multiple operands including a first operand and a second operand, the first operand including a vector of one-hot coded weights and the second operand including a vector of input data, the vector of input data including integer input activation data for a layer of a neural network;

executing the single decoded instruction, wherein executing the single decoded instruction includes:

decoding the one-hot coded weights of the vector of one-hot coded weights; and

performing multiple operations on the decoded one-hot coded weights and the integer input activation data.

16. The method as in claim 15 , wherein each one-hot coded weight in the vector of one-hot coded weights including a sign bit and a power value.

17. The method as in claim 16 , wherein performing the multiple operations includes performing multiple multiply operations.

18. The method as in claim 17 , further comprising performing the multiple multiply operations via vector shift logic of the general-purpose graphics processing unit.

19. The method as in claim 18 , further comprising shifting, via the vector shift logic, each element in the vector of input data by a power value of a corresponding one-hot coded weight.

20. The method as in claim 19 , wherein the vector shift logic includes right-shift logic and the method further comprises right-shifting each element in the vector of input data by a power value of a corresponding one-hot coded weight.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2020
From: LI, JIANGUO; CHEN, YURONG
To: INTEL CORPORATION
Reel/Frame 052080/0879 →
Continuity (1)
Related Publication 20200159534A1 · May 21, 2020