Split direct memory access (DMA) with streaming interconnect

1. An integrated circuit, comprising:

first and second memory devices;

first and second bridges;

a first interconnect segment coupled between the first memory device and the first bridge;

a second interconnect segment coupled between the first and second memory devices;

a first direct memory access (DMA) circuit coupled to the first interconnect segment;

a second DMA circuit coupled to the second interconnect segment; and

a third interconnect segment coupled between the first and second DMA circuits.

2. The integrated circuit of claim 1 , wherein the third interconnect segment comprises a streaming interconnect.

3. The integrated circuit of claim 1 , wherein the third interconnect segment is configured to implement a non-blocking protocol.

4. The integrated circuit of claim 1 , wherein the integrated circuit is a system on a chip (SoC).

5. The integrated circuit of claim 1 , wherein the first DMA circuit includes at least one of a first read engine and a first write engine, and the second DMA circuit includes at least one of a second read engine and a second write engine.

6. The integrated circuit of claim 3 , wherein the first and second interconnect segments are configured to implement blocking protocols.

7. An integrated circuit, comprising:

first and second memory devices;

a bridge;

a first interconnect segment coupled between the first memory device and the bridge;

a second interconnect segment coupled between the first and second memory devices;

a first direct memory access (DMA) circuit coupled to the first interconnect segment;

a second DMA circuit coupled to the second interconnect segment; and

a third interconnect segment coupled between the first and second DMA circuits.

8. The integrated circuit of claim 7 , wherein the bridge is a first bridge coupled between the first and second interconnect segments, and the integrated circuit further comprises a second bridge.

9. The integrated circuit of claim 7 , wherein the third interconnect segment comprises a streaming interconnect.

10. The integrated circuit of claim 7 , wherein the third interconnect segment is configured to implement a non-blocking protocol.

11. The integrated circuit of claim 7 , wherein the integrated circuit is a system on a chip (SoC).

12. The integrated circuit of claim 7 , wherein the first DMA circuit includes at least one of a first read engine and a first write engine, and the second DMA circuit includes at least one of a second read engine and a second write engine.

13. The integrated circuit of claim 10 , wherein the first and second interconnect segments are configured to implement blocking protocols.

14. A device comprising:

first and second devices;

a first interconnect coupled between the first device and the second device;

first and second direct memory access devices coupled to the first interconnect; and

a second interconnect coupled between the first direct memory access device and the second direct memory access device such that the second interconnect is in parallel with the first interconnect,

wherein a communication pathway between the first direct memory access device and the second direct memory access device includes the second interconnect, and

wherein the communication pathway does not include the first interconnect segment or a bridge.

15. The device of claim 14 , wherein the first interconnect includes:

a first interconnect segment coupled between the first device and the first direct memory access device; and

a second interconnect segment coupled between the second device and the second direct memory access device.

16. The device of claim 14 , wherein the first interconnect uses a first protocol and the second interconnect uses a second protocol that is different from the first protocol.

17. The device of claim 14 , wherein the second interconnect is a streaming interconnect.

18. The device of claim 15 , wherein the first interconnect further includes at least one element from a group consisting of an interconnect segment and the bridge coupled between the first interconnect segment and the second interconnect segment.

19. The device of claim 15 , wherein each of the first interconnect segment and the second interconnect segment includes a switch.

20. The device of claim 16 , wherein the first protocol is a blocking protocol and the second protocol is a non-blocking protocol.