IP Library › Granted Patent US 11,481,348
Granted Patent B2
US 11,481,348 · App. 17/161,303 · Granted Oct 25, 2022

Handling operation collisions in a non-volatile memory

Inventors: Lyle E. Adams (San Jose, CA); Mark Ish (San Ramon, CA); Pushpa Seetamraju (San Jose, CA); Karl D. Schuh (Santa Cruz, CA); Dan Tupy (Roseville, CA)
Assignee: MICRON TECHNOLOGY, INC.
G06F13/376G06F3/061G06F3/067G06F3/0659G06F13/1631G06F13/1673
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,481,348
App. No.
17/161,303
Granted
Oct 25, 2022
Kind
B2
Abstract

A first operation identifier is assigned to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier. It is determined whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier. A latest flag is updated to indicate that the first entry is a latest operation directed to an address (1) in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, or (2) in response to determining to determining that the current operation does not collide with a prior operation.

Claims (41)

1. A method comprising:

assigning a first operation identifier to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier;

determining whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier; and

updating, in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, the entry in the first data structure associated with the second operation identifier to identify the first operation identifier.

2. The method of claim 1 , wherein the determining whether the current operation collides with the prior operation comprises checking a second data structure for an entry that has an address value that matches the address to which the current operation is directed.

3. The method of claim 1 , further comprising incrementing a counter associated with the first buffer identifier.

4. The method of claim 1 , wherein the first data structure is stored in a memory outside of the memory component.

5. The method of claim 1 , further comprising:

assigning a third operation identifier to a subsequent operation directed to a memory component, the third operation identifier having a third entry in the first data structure that associates the third operation identifier with a third buffer identifier; and

updating, in response to determining that the subsequent operation collides with the current operation and that the subsequent operation is a read operation, the third buffer identifier to include the first buffer identifier associated with the current operation.

6. The method of claim 5 , wherein the updating comprises replacing the third buffer identifier with the first buffer identifier.

7. The method of claim 1 , further comprising:

updating a latest flag to indicate that the first entry is a latest operation directed to an address.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

assign a first operation identifier to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier;

determine whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier; and

update, in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, the entry in the first data structure associated with the second operation identifier to identify the first operation identifier.

9. The non-transitory computer-readable storage medium of claim 8 , wherein the determining whether the current operation collides with the prior operation comprises checking a second data structure for an entry that has an address value that matches the address to which the current operation is directed.

10. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to increment a counter associated with the first buffer identifier.

11. The non-transitory computer-readable storage medium of claim 8 , wherein the first data structure is stored in a memory outside of the memory component.

12. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:

assign a third operation identifier to a subsequent operation directed to a memory component, the third operation identifier having a third entry in the first data structure that associates the third operation identifier with a third buffer identifier; and

update, in response to determining that the subsequent operation collides with the current operation and that the subsequent operation is a read operation, the third buffer identifier to include the first buffer identifier associated with the current operation.

13. The non-transitory computer-readable storage medium of claim 12 , wherein the updating comprises replacing the third buffer identifier with the first buffer identifier.

14. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:

update a latest flag to indicate that the first entry is a latest operation directed to an address.

15. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

assign a first operation identifier to a current operation directed to a memory component, the first operation identifier having a first entry in a first data structure that associates the first operation identifier with a first buffer identifier;

determine whether the current operation collides with a prior operation assigned a second operation identifier, the second operation identifier having a second entry in the first data structure that associates the second operation identifier with a second buffer identifier;

update, in response to determining that the current operation collides with the prior operation and that the current and prior operations are read operations, the entry in the first data structure associated with the second operation identifier to identify the first operation identifier; and

increment a counter associated with the first buffer identifier.

16. The system of claim 15 , wherein the determining whether the current operation collides with the prior operation comprises checking a second data structure for an entry that has an address value that matches the address to which the current operation is directed.

17. The system of claim 15 , wherein the first data structure is stored in a memory outside of the memory component.

18. The system of claim 15 , wherein the processing device is further to:

assign a third operation identifier to a subsequent operation directed to a memory component, the third operation identifier having a third entry in the first data structure that associates the third operation identifier with a third buffer identifier; and

update, in response to determining that the subsequent operation collides with the current operation and that the subsequent operation is a read operation, the third buffer identifier to include the first buffer identifier associated with the current operation.

19. The system of claim 18 , wherein the updating comprises replacing the third buffer identifier with the first buffer identifier.

20. The system of claim 15 , wherein the processing device is further to:

update a latest flag to indicate that the first entry is a latest operation directed to an address.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2021
From: ADAMS, LYLE E.; ISH, MARK; SEETAMRAJU, PUSHPA; SCHUH, KARL D.; TUPY, DAN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 055068/0914 →
Continuity (4)
Continuation 16886656 · May 28, 2020
Continuation 16693801 · Nov 25, 2019
Continuation 16223057 · Dec 17, 2018
Related Publication 20210182227A1 · Jun 17, 2021
Cited By (1)
US 12,613,658