Integrated circuit with P-N-P junction and vertically aligned field effect transistor, and method to form same
Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a p-type substrate, a p-well region within the p-type substrate, and an n-type barrier region between the p-type substrate and the p-well region. The n-type barrier region physically isolates the p-type substrate from the p-well region. A field effect transistor (FET) is positioned above the p-well region, and a buried insulator layer on the upper surface of the p-well region separates the transistor from the p-well region. A first voltage source electrically coupled to the p-well region induces a P-N-P junction across the p-well region, the n-type barrier region, and the p-type substrate.
1. An integrated circuit (IC) structure, comprising:
a p-type substrate;
a p-well region within the p-type substrate;
an n-type barrier region between the p-type substrate and the p-well region, wherein the n-type barrier region physically isolates the p-type substrate from the p-well region;
a field effect transistor (FET) above the p-well region, wherein a buried insulator layer separates the FET from the p-well region, and an upper surface of the n-type barrier region is substantially coplanar with an upper surface of the buried insulator layer; and
a first voltage source electrically coupled to the p-well region inducing a P-N-P junction across the p-well region, the n-type barrier region, and the p-type substrate,
wherein the p-well region defines an emitter terminal of a bipolar junction transistor (BJT), the n-type barrier region defines a base terminal of the BJT, and the p-type substrate defines a collector terminal of the BJT,
wherein the first voltage source concurrently applies a forward bias to the p-well region and applies a back-gate bias to the FET to adjust a threshold voltage of the FET.
2. The IC structure of claim 1 , wherein the p-well region has an upper surface substantially aligned with an upper surface of the p-type substrate.
3. The IC structure of claim 1 , wherein the P-N-P junction is oriented substantially perpendicularly with respect to a channel region of the FET.
4. The IC structure of claim 1 , further comprising:
a second voltage source coupled to the n-type barrier region; and
a third voltage source coupled to the p-type substrate.
5. The IC structure of claim 1 , wherein the P-N-P junction forms the bipolar junction transistor (BJT) within the p-type substrate.
6. The IC structure of claim 4 , wherein the P-N-P junction forms the bipolar junction transistor (BJT) within the p-type substrate and wherein the first voltage source is electrically coupled to the p-well through an emitter contact of the BJT, the second voltage source is electrically coupled to the n-type barrier region through a base contact of the BJT, and the third voltage source is electrically coupled to the p-type substrate through a collector contact of the BJT.
7. The IC structure of claim 4 , wherein the second voltage source applies a first reverse bias to the n-type barrier region concurrently with the forward bias, and wherein the third voltage source applies a second reverse bias to the p-type substrate concurrently with the forward bias.
8. The IC structure of claim 1 , further comprising a plurality of trench isolations that extend through the buried insulator layer and at least partially into the p-well region.
9. The IC structure of claim 1 , wherein the back-gate bias to the FET is a positive voltage bias.
10. An integrated circuit (IC) structure comprising:
a bipolar junction transistor (BJT) including:
a p-type substrate;
a p-well region within the p-type substrate;
an n-type barrier region between the p-type substrate and the p-well region, wherein the n-type barrier region physically isolates the p-type substrate from the p-well region;
a first voltage source electrically coupled to the p-well region inducing a P-N-P junction across the p-well region, the n-type barrier region, and the p-type substrate;
a buried insulator layer above the p-well region of the BJT, wherein an upper surface of the buried insulator layer is substantially coplanar with an upper surface of the n-type barrier region; and
a field effect transistor (FET) on the buried insulator layer above the p-well region, and including a semiconductor channel region above the buried insulator layer, wherein the semiconductor channel is positioned vertically above the P-N-P junction,
wherein the p-well region defines an emitter terminal of the BJT, the n-type barrier region defines a base terminal of the BJT, and the p-type substrate defines a collector terminal of the BJT,
wherein the first voltage source concurrently applies a forward bias to the p-well region and applies a back-gate bias to the FET to adjust a threshold voltage of the FET.
11. The IC structure of claim 10 , wherein the p-well region has an upper surface substantially aligned with an upper surface of the p-type substrate.
12. The IC structure of claim 10 , wherein the P-N-P junction is oriented substantially perpendicularly with respect to the semiconductor channel of the FET.
13. The IC structure of claim 10 , wherein the BJT further includes:
a second voltage source coupled to the n-type barrier region; and
a third voltage source coupled to the p-type substrate.
14. The IC structure of claim 13 , wherein the first voltage source is electrically coupled to the p-well through an emitter contact of the BJT, the second voltage source is electrically coupled to the n-type barrier region through a base contact of the BJT, and the third voltage source is electrically coupled to the p-type substrate through a collector contact of the BJT.
15. The IC structure of claim 10 , wherein the FET further includes:
a gate stack defining a gate terminal of the FET; and
a source/drain contact defining a source terminal or a drain terminal of the FET,
wherein the first voltage source operates independently of the gate stack and the source/drain contact.
16. A method to form a bipolar junction transistor (BJT) in vertical alignment with a field effect transistor (FET), the method comprising:
providing a structure including:
a p-type substrate,
a p-well region within the p-type substrate,
an n-type barrier region between the p-type substrate and the p-well region, wherein the n-type barrier region physically isolates the p-type substrate from the p-well region,
a buried insulator layer above the substrate, wherein an upper surface of the buried insulator layer is substantially coplanar with an upper surface of the n-type barrier region, and
a field effect transistor (FET) above the buried insulator layer;
applying a first voltage to concurrently apply a forward bias to the p-well region and apply a back-gate bias to the FET to adjust a threshold voltage of the FET, wherein applying the forward bias induces a P-N-P junction across the p-well region, the n-type barrier region, and the p-type substrate,
wherein the p-well region defines an emitter terminal of the BJT, the n-type barrier region defines a base terminal of the BJT, and the p-type substrate defines a collector terminal of the BJT.
17. The method of claim 16 , wherein applying the forward bias causes the P-N-P junction to be oriented substantially perpendicularly with respect to a channel region of the FET.
18. The method of claim 16 , further comprising
applying a first reverse bias to the n-type barrier region concurrently with the forward bias; and
applying a second reverse bias to the p-type substrate concurrently with the forward bias.
19. The method of claim 16 , wherein the first reverse bias enables current flow across the n-type barrier region between the p-well region and the p-type substrate.
20. The method of claim 16 , further comprising applying a gate bias to the FET, wherein the gate bias is independent of the forward bias.