Semiconductor devices including a narrow active pattern

1. A semiconductor device comprising:

a substrate;

a first gate structure extending in a first direction, in a first region of the substrate;

first active patterns penetrating through the first gate structure and having a first width in the first direction and a first height in a second direction, the first width being smaller than the first height;

a first source/drain region electrically connected to the first active patterns;

a second gate structure extending in a third direction, in a second region of the substrate;

second active patterns penetrating through the second gate structure and having a second width in the third direction and a second height in a fourth direction, the second height being different from the first height;

a second source/drain region electrically connected to the second active patterns; and

a first spacer between the second gate structure and the second source/drain region, and between the second active patterns and the substrate, and including the same material as the second source/drain region,

wherein the first spacer is not between the first gate structure and the first source/drain region, and is not between the first active patterns and the substrate, and

wherein the number of the first active patterns is equal to the number of the second active patterns.

2. The semiconductor device of claim 1 ,

wherein the first gate structure comprises a first gate insulating film extending around the first active patterns, and a first gate electrode on the first gate insulating film,

wherein a sidewall of the first gate structure that faces the first source/drain region is longer in the second direction than in the first direction,

wherein the second gate structure comprises a second gate insulating film extending around the second active patterns, and a second gate electrode on the second gate insulating film, and

wherein a sidewall of the second gate structure that faces the second source/drain region is longer in the fourth direction than in the third direction.

3. The semiconductor device of claim 1 ,

wherein the first active patterns include a first sub active pattern and a second sub active pattern spaced apart from the first sub active pattern in the second direction and penetrating through the first gate structure; and

wherein the second active patterns include a third sub active pattern and a fourth sub active pattern spaced apart from the third sub active pattern in the fourth direction and penetrating through the second gate structure.

4. The semiconductor device of claim 3 , wherein a first distance between the first sub active pattern and the second sub active pattern is equal to a second distance between the third sub active pattern and the fourth sub active pattern.

5. The semiconductor device of claim 1 ,

wherein the first active patterns include a first sub active pattern and a second sub active pattern spaced apart from the first sub active pattern in the first direction and penetrating through the first gate structure.

6. The semiconductor device of claim 5 ,

wherein the second active patterns include a third sub active pattern and a fourth active pattern spaced apart from the third sub active pattern in the third direction and penetrating through the second gate structure.

7. The semiconductor device of claim 1 ,

a third source/drain region spaced apart from the first source/drain region and electrically connected to the first active patterns,

wherein a first thickness of the first source/drain region in the second direction is different from a second thickness of the third source/drain region in the second direction.

8. The semiconductor device of claim 7 ,

wherein the first active patterns include a first sub active pattern and a second sub active pattern spaced apart from the first sub active pattern in the second direction and penetrating through the first gate structure,

wherein the first source/drain region is in contact with the first sub active pattern and the second sub active pattern, and

wherein the third source/drain region is in contact with the first active sub pattern and is not in contact with the second sub active pattern.

9. The semiconductor device of claim 1 , wherein the second width is greater than the second height.

10. The semiconductor device of claim 9 ,

wherein the first active patterns include a first sub active pattern and a second sub active pattern penetrating through the first gate structure on the first active patterns;

wherein the second active patterns include a third sub active pattern and a fourth sub active pattern penetrating through the second gate structure on the second active patterns; and

wherein the second active patterns further include a fifth sub active pattern penetrating through the second gate structure on the fourth sub active pattern.

11. The semiconductor device of claim 10 , wherein a first distance between a lower surface of the first sub active pattern and an upper surface of the second sub active pattern is equal to a second distance between a lower surface of the third sub active pattern and an upper surface of the fifth sub active pattern.

12. The semiconductor device of claim 9 ,

wherein the second width is equal to the first height, and

wherein the second height is equal to the first width.

13. The semiconductor device of claim 1 , wherein the second width is smaller than the second height, and the second height is smaller than the first height.

14. A semiconductor device comprising:

a substrate including first and second regions;

a first gate structure extending in a first direction, in the first region;

a first active pattern intersecting the first gate structure and having a first width in the first direction and a first height in a second direction, the first width being smaller than the first height, wherein the first active pattern is an active pattern of a PMOS transistor;

a first source/drain region electrically connected to the first active pattern;

a second gate structure extending in a third direction, in the second region;

a second active pattern penetrating through the second gate structure and having a second width in the third direction and a second height in a fourth direction, the second width being smaller than the second height, and the second height being smaller than the first height, wherein the second active pattern is an active pattern of an NMOS transistor; and

a second source/drain region electrically connected to the second active pattern,

wherein an upper surface of the first source/drain region is higher than an upper surface of the second source/drain region.

15. The semiconductor device of claim 14 ,

wherein a sidewall of the first gate structure that faces the first source/drain region is longer in the second direction than in the first direction, and

wherein the first gate structure comprises a gate structure of a nanosheet transistor.

16. The semiconductor device of claim 15 ,

wherein the first gate structure comprises a first gate insulating film extending along a sidewall of the first active pattern, and a first gate electrode on the first gate insulating film, and

wherein the second gate structure comprises a second gate insulating film extending around the second active pattern, and a second gate electrode on the second gate insulating film.

17. The semiconductor device of claim 15 , wherein the first active pattern comprises first and second semiconductor patterns alternately stacked.

18. The semiconductor device of claim 14 , further comprising:

a third active pattern spaced apart from the first active pattern in the second direction and intersecting the first gate structure,

wherein the third active pattern is another active pattern of the PMOS transistor.

19. A semiconductor device comprising:

a substrate;

first and second active patterns extending in a first direction on the substrate and having a width in a second direction and a height in a third direction, the first and second active patterns being spaced apart from each other in the third direction by a distance;

a gate structure extending in the second direction and intersecting the first and second active patterns, wherein the gate structure is between the substrate and the first active pattern, between the first active pattern and the second active pattern, and on the second active pattern;

a source/drain region electrically connected to the first and second active patterns; and

a source/drain contact electrically connected to the source/drain region, extending in the third direction, and not overlapping the first and second active patterns in the first direction,

wherein the width is smaller than the height, and

wherein, in a cross section taken along the second direction, a distance between an upper surface of the substrate and the first active pattern is equal to a distance between the first active pattern and the second active pattern.

20. The semiconductor device of claim 19 , wherein the source/drain contact includes a contact layer in contact with the source/drain region, a metal barrier on the contact layer, and metal material in a region defined by the contact layer and the metal barrier.