IP Library › Granted Patent US 11,486,767
Granted Patent B2
US 11,486,767 · App. 17/189,140 · Granted Nov 1, 2022

Semiconductor storage device, method of controlling semiconductor storage device, and memory system

Inventors: Keisuke Terada (Kamakura Kanagawa, JP); Eietsu Takahashi (Yokohama Kanagawa, JP)
Assignee: KIOXIA CORPORATION
G01K1/022G11C16/16G11C16/26G11C16/3445G11C16/3459
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Quick Facts
Patent No.
US 11,486,767
App. No.
17/189,140
Granted
Nov 1, 2022
Kind
B2
Abstract

A semiconductor storage device includes a memory cell and a control circuit configured to, upon receipt of a command, acquire a first temperature measured by a temperature sensor, and perform an operation corresponding to the command using a parameter corrected based on temperature. When the first temperature is within a predetermined range with respect to a second temperature measured before the command is received, the parameter is corrected using the second temperature. When the first temperature is outside the predetermined range, the parameter is corrected using the first temperature.

Claims (67)

1. A semiconductor storage device, comprising:

a memory cell; and

a control circuit configured to:

acquire a first temperature measured by a temperature sensor upon receipt of a command; and

perform an operation corresponding to the command using a parameter corrected based on a temperature measured by the temperature sensor, wherein

when the first temperature is within a predetermined range with respect to a second temperature measured before the command is received, the parameter is corrected using the second temperature, and

when the first temperature is outside the predetermined range, the parameter is corrected using the first temperature.

2. The semiconductor storage device according to claim 1 , wherein the control circuit is further configured to:

determine whether the received command is a read command, and

upon determining that the received command is the read command, perform a read operation corresponding to the read command with a read voltage corrected using:

the second temperature when the first temperature is within the predetermined range and

the first temperature when the first temperature is outside the predetermined range.

3. The semiconductor storage device according to claim 2 , wherein, if the received command is not the read command, the controller performs the operation corresponding to the received command with the parameter corrected using the first temperature even if the first temperature is within the predetermined range.

4. The semiconductor storage device according to claim 2 , wherein

the read command is a read command for retry read, and

the parameter is a particular shift amount for a read voltage.

5. The semiconductor storage device according to claim 1 , wherein

the command is a write command, and

the parameter is a verification voltage applied to the memory cell after data is written to the memory cell by a program operation.

6. The semiconductor storage device according to claim 1 , wherein

the command is an erase command, and

the parameter is one of:

an erase voltage applied to the memory cell when data stored in the memory cell is erased, and

a verification voltage applied to the memory cell after the data is erased.

7. The semiconductor storage device according to claim 1 , wherein the temperature sensor is on a semiconductor chip on which the memory cell and the control circuit are mounted.

8. The semiconductor storage device according to claim 1 , further comprising:

a first register that stores the first temperature; and

a second register that stores the second temperature.

9. The semiconductor storage device according to claim 8 , wherein the control circuit is further configured to store codes corresponding to the first and second temperatures in the first and second registers.

10. The semiconductor storage device according to claim 1 , further comprising:

an interface circuit through which the command is received from a memory controller including the temperature sensor.

11. A method of controlling a semiconductor storage device, the method comprising:

acquiring a first temperature measured by a temperature sensor upon receipt of a command; and

performing an operation corresponding to the received command using a parameter corrected for temperature, wherein

when the first temperature is within a predetermined range with respect to a second temperature measured before the command is received, the parameter is corrected using the second temperature, and

when the first temperature is outside the predetermined range, the parameter is corrected using the first temperature.

12. The method according to claim 11 , further comprising:

determining whether the received command is a read command, wherein

when the received command is the read command, performing a read operation corresponding to the read command with a read voltage corrected using:

the second temperature when the first temperature is within the predetermined range and

the first temperature when the first temperature is outside the predetermined range.

13. The method according to claim 12 , wherein, if the received command is not the read command, the operation corresponding to the received command is performed with the parameter corrected using the first temperature even if the first temperature is within the predetermined range.

14. The method according to claim 12 , wherein

the read command is a read command for retry read, and

the parameter is a particular shift amount for a read voltage.

15. The method according to claim 11 , wherein

the command is a write command, and

the parameter is a verification voltage applied to a memory cell after data is written to the memory cell by a program operation.

16. The method according to claim 11 , wherein

the command is an erase command, and

the parameter indicates is of:

an erase voltage applied to a memory cell when data stored in the memory cell is erased, and

a verification voltage applied to the memory cell after the data is erased.

17. The method according to claim 11 , wherein the temperature sensor is in the semiconductor storage device.

18. The method according to claim 11 , further comprising:

storing the first temperature in a first register; and

storing the second temperature in a second register.

19. The method according to claim 18 , wherein codes corresponding to the first and second temperatures are stored in the first and second registers.

20. A memory system, comprising:

a controller configured to issue a command; and

a semiconductor storage device including:

a memory cell, and

a control circuit configured to:

acquire a first temperature measured by a temperature sensor upon receipt of the command from the controller; and

perform an operation corresponding to the command using a parameter corrected based on a temperature, wherein

when the first temperature is within a predetermined range with respect to a second temperature measured before the command is received, the parameter is corrected using the second temperature, and

when the first temperature is outside the predetermined range, the parameter is corrected using the first temperature.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2022
From: TERADA, KEISUKE; TAKAHASHI, EIETSU
To: KIOXIA CORPORATION
Reel/Frame 059578/0921 →
Priority Claims (1)
JP JP2020-142881 · Aug 26, 2020 · national
Continuity (1)
Related Publication 20220065702A1 · Mar 3, 2022
Cited By (1)
US 12,586,657