Techniques for configuring a processor to execute instructions efficiently
Systems and techniques for improving the performance of circuits while adapting to dynamic voltage drops caused by the execution of noisy instructions (e.g. high power consuming instructions) are provided. The performance is improved by slowing down the frequency of operation selectively for types of noisy instructions. An example technique controls a clock by detecting an instruction of a predetermined noisy type that is predicted to have a predefined noise characteristic (e.g. a high level of noise generated on the voltage rails of a circuit due to greater amount of current drawn by the instruction), and, responsive to the detecting, deceasing a frequency of the clock. The detecting occurs before execution of the instruction. The changing of the frequency in accordance with instruction type enables the circuits to be operated at high frequencies even if some of the workloads include instructions for which the frequency of operation is slowed down.
1. A method of controlling a clock of a processor, comprising:
detecting an instruction that is predicted to have a predefined noise characteristic, the detecting occurring before execution of the instruction by the processor; and
responsive to the detecting, changing a frequency of the clock,
wherein the changing the frequency includes decreasing the frequency by an offset determined to compensate for a predicted drop in voltage corresponding to the predefined noise characteristic, and
wherein the offset is determined from a programmable mapping of instructions to frequency offset amounts.
2. The method according to claim 1 , wherein the changing the frequency includes decreasing the frequency by an offset determined to compensate for a predicted drop in voltage corresponding to the predefined noise characteristic.
3. The method according to claim 2 , the method further comprises:
executing the instruction at least partially while the clock operates at the decreased frequency; and
increasing the frequency of the clock after the executing.
4. The method according to claim 3 , further comprising subjecting the increasing to a hysteresis process.
5. The method according to claim 4 , wherein the decreasing is performed without being subject to a hysteresis process.
6. The method according to claim 1 , wherein the detecting includes, determining that a type of the instruction matches a type in a predetermined set of instruction types.
7. The method according to claim 6 , wherein the predetermined set of instruction types include at least one high power instruction type that is predicted to consume more than a threshold level of power.
8. The method according to claim 1 , further comprising:
configuring the clock to operate at a default frequency, and
wherein said detecting occurs while the clock is operating at the default frequency, wherein the default frequency is determined in accordance with other instructions that are predicted to have a lower noise level than the detected instruction.
9. The method according to claim 1 , wherein the detecting occurs during decoding of the instruction, and the changing occurs before the decoded instruction is executed by the processor.
10. The method according to claim 9 , further comprising:
in response to the detecting, stalling the instruction before its execution; and
unstalling the instruction in response to the frequency being changed or a timer signal.
11. The method according to claim 1 , wherein changing the frequency of the clock comprises changing a frequency of the clock source within a predetermined fixed number of clock cycles after receiving a clock change signal at the clock source.
12. The method according to claim 11 , wherein changing the frequency of the clock further comprises identifying a target frequency from a lookup table, and setting the clock source to the target frequency.
13. The method according to claim 12 , wherein the changing the frequency of the clock further includes adjusting the frequency in accordance with a noise aware frequency locked loop technique.
14. A method of controlling a clock of a processor, comprising:
detecting an instruction that is predicted to have a predefined noise characteristic, the detecting occurring before execution of the instruction by the processor; and
responsive to the detecting, changing a frequency of the clock,
wherein the detecting includes, determining that a type of the instruction matches a type in a predetermined set of instruction types,
wherein the predetermined set of instruction types includes at least two groups of instruction types, with each of the two groups having a mapping to a respective frequency offset amount,
wherein the detecting further comprises determining which of the at least two groups to which the instruction belongs, and
wherein the changing further comprises adjusting the frequency in accordance with the respective frequency offset amount mapped to the determined one of the at least two groups.
15. The method of claim 14 , wherein at least one of a composition of the at least two groups or the respective frequency amounts is programmable.
16. A system comprising processing circuitry and a clock generator controlling a frequency of operation of the processing circuitry, the processing circuitry configured to:
detect an instruction that is predicted to have a predefined noise characteristic, the detecting occurring before execution of the instruction in the processing circuitry; and
responsive to the detecting, signaling the clock generator to change a frequency of the clock generator,
wherein the system further comprises a mapping from a type of the instruction to a frequency offset amount determined to compensate for a predicted drop in voltage corresponding to the predefined noise characteristic, and
wherein the signaling comprises including the frequency offset amount in the signaling.
17. The system according to claim 16 , wherein the detecting is performed during decoding of the instruction, and the processing circuitry is further configured to execute the instruction after said changing the frequency.
18. The system according to claim 16 , wherein the detecting includes, determining that a type of the instruction matches a type in a predetermined set of instruction types.
19. The system according to claim 16 , wherein changing the frequency comprises changing a frequency of a clock source within a predetermined fixed number of clock cycles after receiving a clock change signal at the clock generator.
20. The system according to claim 19 , wherein changing the frequency further comprises identifying a target frequency from a lookup table, and setting the clock source to the target frequency.
21. The system according to claim 20 , wherein the changing the frequency further includes adjusting the frequency in accordance with a noise aware frequency locked loop (NAFLL) technique.
22. The system according to claim 16 , wherein the processing circuitry includes an instruction pipeline which is configured to block execution of the instruction until a predetermined signal is received from the clock generator or a timer.
23. The system according to claim 16 , wherein the system further comprises a plurality of processing cores including said processing circuitry, wherein each of the processor cores receive the frequency from the clock generator, and wherein the clock generator is configured to:
receive signals from one or more of the plurality of processor cores, and
change the frequency in accordance with a selected subset of the received signals.
24. The system according to claim 16 , wherein the processing circuitry and the clock generator are formed on an integrated circuit.
25. A system comprising processing circuitry and a clock generator controlling a frequency of operation of the processing circuitry, the processing circuitry configured to:
detect an instruction that is predicted to have a predefined noise characteristic, the detecting occurring before execution of the instruction in the processing circuitry; and
responsive to the detecting, signal the clock generator to change a frequency of the clock generator,
wherein the detecting includes, determining that a type of the instruction matches a type in a predetermined set of instruction types,
further comprises at least a first signaling path and a second signaling path between the processing circuitry and the clock generator, wherein the predetermined set of instruction types includes at least first and second groups of instruction types associated respectively with the first and second signaling paths, with each of the two groups having a mapping to a respective frequency offset amount,
wherein the detecting further comprises determining which of the at least two groups to which the instruction belongs, and
wherein the changing further comprises adjusting the frequency in accordance with the respective frequency offset amount mapped to the determined one of the at least two groups.