Semiconductor storing apparatus and readout method
A semiconductor storing apparatus capable of shortening a ECC processing time of a readout operation is provided, including a flash memory includes: a memory cell array; a page buffer/sense circuit holding data read out from a selected page of the memory cell array; an error correcting code circuit receiving data from the page buffer/sense circuit and holding error address information of the data; an output circuit selecting data from the page buffer/sense circuit based on a column address, and outputting the selected data to a data bus; and an error correction part correcting data of the data bus based on the error address information.
1. A semiconductor storing apparatus, comprising:
a memory cell array;
a page buffer/sense circuit, holding data read from a selected page of the memory cell array;
an error correcting code (ECC) circuit, receiving the data that is held in the page buffer/sense circuit and detecting the data, and holding error address information related to an error address that is detected;
an output circuit, selecting the data from the page buffer/sense circuit based on a column address, and outputting the selected data to a data bus; and
an error correction part, correcting the data on the data bus based on the error address information.
2. The semiconductor storing apparatus according to claim 1 , wherein
the error correction part comprises an inversion circuit that inverts the data on the data bus based on the error address information.
3. The semiconductor storing apparatus according to claim 2 , wherein
the error correction part comprises an address comparison part that compares the error address information with the column address, and corrects the data on the data bus corresponding to an error bit address based on a comparison result.
4. The semiconductor storing apparatus according to claim 1 , wherein
the ECC circuit detects an address of a multi-bit error.
5. The semiconductor storing apparatus according to claim 1 , wherein
the error correction part is implemented when the page is continuously read.
6. The semiconductor storing apparatus according to claim 5 , wherein
the page buffer/sense circuit has a first latch for holding the data in the page read from the memory cell array, and a second latch for receiving the data in the page held by the first latch, each of the first latch and the second latch comprises a first part and a second part capable of performing data transmission independently, the first part and the second part capable of holding ½ page of the data,
when the page is continuously read, while data of the first part of the second latch is output to the outside, error detection and correction is performed on data of the second part of the second latch, while the data of the second part of the second latch is output to the outside, error detection and correction is performed on the data of the first part of the second latch.
7. The semiconductor storing apparatus according to claim 6 , wherein
when the page is continuously read, the data is output to the outside in synchronization with a clock signal input from the outside.
8. The semiconductor storing apparatus according to claim 7 , wherein
the continuous reading of the page satisfies the condition of tPRE+tDIS+tECC<tDOUT (tPRE is a precharge time of bit line, tDIS is a discharge time of a memory cell, tECC is the time for error detection and correction of ½ page, and tDOUT is data output time of one page).
9. The semiconductor storing apparatus according to claim 3 , wherein
the output circuit supplies n bit data selected from the page buffer/sense circuit to n differential sense amplifiers, and the error correction part inverts the data output from the differential sense amplifier.
10. The semiconductor storing apparatus according to claim 9 , wherein
the n bit data sensed by the differential sense amplifier are respectively input to one input of n exclusive or gate of the inversion circuit, and the other input of the n exclusive or gate is respectively input with an inversion control signal from the address comparison part.
11. A readout method, which is a readout method for flash memory, and the readout method comprising the following steps:
during a read operation, receiving data held in a page buffer/sense circuit, detecting the data;
holding error address information related to an error address that is detected;
selecting the data from the page buffer/sense circuit based on a column address, and outputting the selected data to a data bus;
correcting the data on the data bus based on the error address information; and
outputting the corrected data to the outside.
12. The readout method according to claim 11 , wherein
the correction step is to compare the error address information with the column address, and invert the data on the data bus corresponding to an error bit address based on a comparison result.
13. The readout method according to claim 11 , wherein
when a read command is received, it is identified whether the read command is continuous read or page read, if the read command is the continuous read, a controller enables an error correction part through a first enable signal to correct the data output from the page buffer/sense circuit to the data bus.
14. The readout method according to claim 13 , wherein
if the read command is the page read, the controller disables the error correction part through the first enable signal, and enables a write circuit through a second enable signal, when the error correction part is disabled, all of inversion control signals are set to a first level, so that the data on the data bus pass directly.