Delaying anode voltage reset for quicker response times in OLED displays
This document describes systems and techniques for delaying anode voltage reset for quicker response times in organic light-emitting diode (OLED) displays. In an aspect, a pixel circuit includes a transistor electrically connected to an anode of an organic light-emitting diode and a reset voltage. Upon receiving an anode reset signal, the transistor completes the circuit causing the anode voltage to reset to the reset voltage in an anode voltage reset process. Delaying anode voltage reset can hasten response times in OLED displays.
1. A display comprising:
a pixel array including multiple pixel circuits, each of the multiple pixel circuits connected to an emission-control line, a data line, a scan line, and an anode reset line;
an emission-control driver configured to generate and supply an emission-control signal, through the emission-control line, to the one or more pixel circuits of the multiple pixel circuits, the emission-control signal configured to produce a first emission cycle and a second emission cycle;
a data-line driver configured to generate and supply a data signal, through the data line, to the one or more pixel circuits of the multiple pixel circuits during at least one of the first emission cycle or the second emission cycle;
a scan-line driver configured to generate and supply a scan signal, through the scan line, to the one or more pixel circuits of the multiple pixel circuits during at least one of the first emission cycle or the second emission cycle; and
the scan-line driver further configured to:
generate and supply an anode reset signal during the second emission cycle, through the scan line or an anode reset line, to the one or more pixel circuits of the multiple pixel circuits, the anode reset signal configured to:
reset, during a display-frame period, an anode voltage of the one or more pixel circuits of the multiple pixel circuits to a reset voltage less than a threshold voltage, the reset of the anode voltage being delayed until the second emission cycle effective to decrease a delay in an emission of light by the one or more of the multiple pixel circuits.
2. The display of claim 1 , wherein the display-frame period comprises two emission cycles.
3. The display of claim 2 , wherein the reset of the anode voltage is delayed ½ of the display-frame period.
4. The display of claim 1 , wherein the display-frame period comprises four emission cycles.
5. The display of claim 4 , wherein the scan-line driver is further configured to generate and supply a second anode reset signal during a fourth emission cycle.
6. The display of claim 5 , wherein the reset of the anode voltage is delayed ¼ of the display-frame period.
7. The display of claim 1 , wherein the display-frame period comprises six emission cycles.
8. The display of claim 7 , wherein the scan-line driver is further configured to generate and supply an anode reset signal for at least one of a fourth emission cycle or a sixth emission cycle.
9. The display of claim 8 , wherein the reset of the anode voltage is delayed at least ⅙ of the display-frame period.
10. The display of claim 1 , wherein the reset of the anode voltage is delayed until during the second emission cycle, the reset of the anode voltage being for a variable duration during the second emission cycle.
11. The display of claim 10 , wherein the variable duration is based at least in part on a data voltage of the data signal generated and supplied by the data-line driver.
12. The display of claim 1 , further comprising an additional driver, the additional driver configured to supply, to the scan-line driver, the anode reset signal.
13. The display of claim 1 , wherein the display comprises an organic light-emitting diode (OLED) display.