Semiconductor memory device including page buffers

1. A semiconductor memory device comprising:

a latch defined on a circuit chip;

a bit line select transistor defined in a first memory chip stacked on the circuit chip; and

a bit line select transistor defined in a second memory chip stacked on the first memory chip,

wherein the bit line select transistors exchange data with the latch,

wherein each of the first and second memory chips further includes:

a coupling capacitor including a bit line, a wiring line that overlaps with the bit line and a dielectric layer disposed between the bit line and the wiring line; and

a first erase voltage pass transistor coupled to a source plate and the wiring line, and configured to transfer an erase voltage to the source plate and the wiring line in an erase operation.

2. The semiconductor memory device according to claim 1 , wherein the bit line select transistor of the first memory chip and the bit line select transistor of the second memory chip share a through-chip interconnector disposed to traverse the stacked first and second memory chips.

3. The semiconductor memory device according to claim 1 , wherein the bit line select transistor of the first memory chip and the bit line select transistor of the second memory chip are controlled to be simultaneously turned on or off.

4. The semiconductor memory device according to claim 1 , wherein the bit line select transistor of the first memory chip and the bit line select transistor of the second memory chip are controlled to be individually turned on or off.

5. The semiconductor memory device according to claim 1 ,

wherein each of the first and second memory chips includes a memory cell array coupled between the bit line and the source plate, and

wherein each of the memory cell arrays includes a plurality of memory blocks in which data are stored and is coupled to the first memory chip or the second memory chip, and

wherein each of the first and second memory chips further includes a second erase voltage pass transistor coupled to the bit line to apply the erase voltage to the bit line in the erase operation.

6. The semiconductor memory device according to claim 5 , wherein the second erase voltage pass transistor of the first memory chip and the second erase voltage pass transistor of the second memory chip are controlled to be individually turned on or off in the erase operation, and

wherein the erase voltage is applied to the bit line of a memory chip including a selected memory block and the erase voltage is not applied to the bit line of a memory chip not including the selected memory block.

7. The semiconductor memory device according to claim 1 , wherein each of the first and second memory chips further includes a third erase voltage pass transistor coupled to the source plate that applies the erase voltage to the source plate in the erase operation.

8. The semiconductor memory device according to claim 7 , wherein the third erase voltage pass transistor of the first memory chip and the third erase voltage pass transistor of the second memory chip are controlled to be individually turned on or off, and

wherein, in the erase operation, the erase voltage is applied to the source plate of a memory chip including a selected memory block and the erase voltage is not applied to the source plate of a memory chip not including the selected memory block.

9. The semiconductor memory device according to claim 1 , wherein the first erase voltage pass transistor of the first memory chip and the first erase voltage pass transistor of the second memory chip are controlled to be individually turned on or off, and

wherein, in the erase operation, the erase voltage is applied to the source plate and the wiring line of a memory chip including a selected memory block, and the erase voltage is not applied to the source plate and the wiring line of a memory chip that does not include the selected memory block.

10. A semiconductor memory device comprising:

a bit line select transistor defined in each of a first and a second memory chip, which are stacked on a circuit chip;

a through-chip interconnector traversing the first and second memory chips, and coupled in common to the bit line select transistor of the first memory chip and the bit line select transistor of the second memory chip; and

a latch defined in the circuit chip and, through the through-chip interconnector, coupled to the bit line select transistor of the first memory chip and the bit line select transistor of the second memory chip,

wherein each of the first and second memory chips further includes:

a coupling capacitor including a bit line, a wiring line that overlaps with the bit line and a dielectric layer disposed between the bit line and the wiring line; and

a first erase voltage pass transistor coupled to a source plate and the wiring line, and configured to transfer an erase voltage to the source plate and the wiring line in an erase operation.

11. The semiconductor memory device according to claim 10 , wherein the bit line select transistor of the first memory chip and the bit line select transistor of the second memory chip are controlled to be individually turned on or off.

12. The semiconductor memory device according to claim 10 ,

wherein each of the first and second memory chips includes a memory cell array coupled between the bit line and the source plate,

wherein each of the memory cell arrays includes a plurality of memory blocks in which data are stored and is coupled to the bit line select transistor, and

wherein each of the first and second memory chips further includes a second erase voltage pass transistor coupled to the bit line to apply the erase voltage to the bit line in the erase operation.

13. The semiconductor memory device according to claim 12 , wherein the second erase voltage pass transistor of the first memory chip and the second erase voltage pass transistor of the second memory chip are controlled to be individually turned on or off, and

wherein, in the erase operation, the erase voltage is applied to the bit line of a memory chip including a selected memory block and the erase voltage is not applied to the bit line of a memory chip not including the selected memory block.

14. The semiconductor memory device according to claim 12 , wherein each of the first and second memory chips further includes a third erase voltage pass transistor coupled to the source plate to apply the erase voltage to the source plate in the erase operation.

15. The semiconductor memory device according to claim 14 , wherein the third erase voltage pass transistor of the first memory chip and the third erase voltage pass transistor of the second memory chip are controlled to be individually turned on or off, and

wherein, in the erase operation, the erase voltage is applied to the source plate of a memory chip including a selected memory block and the erase voltage is not applied to the source plate of a memory chip not including the selected memory block.

16. The semiconductor memory device according to claim 10 , wherein the first erase voltage pass transistor of the first memory chip and the first erase voltage pass transistor of the second memory chip are controlled to be individually turned on or off, and

wherein, in the erase operation, the erase voltage is applied to the source plate and the wiring line of a memory chip including a selected memory block, and the erase voltage is not applied to the source plate and the wiring line of a memory chip that does not include the selected memory block.

17. A semiconductor memory device comprising:

low-voltage elements of a page buffer circuit defined on a circuit chip; and

high-voltage elements of the page buffer circuit defined in each of a first memory chip and a second memory chip stacked on the circuit chip,

wherein each of the first and second memory chips includes:

a coupling capacitor including a bit line, a wiring line that overlaps with the bit line and a dielectric layer disposed between the bit line and the wiring line; and

an erase voltage pass transistor coupled to a source plate and the wiring line, and configured to transfer an erase voltage to the source plate and the wiring line in an erase operation.

18. The semiconductor memory device according to claim 17 ,

wherein each of the first and second memory chips includes a memory cell array coupled between the bit line and the source plate,

wherein each of the memory cell arrays is coupled to a bit line select transistor and includes a plurality of memory blocks in which data are stored, and

wherein each of the first and second memory chips further includes an erase circuit, connected to at least one of the bit line and the source plate, which transfers the erase voltage to at least one of the bit line and the source plate in the erase operation.