Semiconductor device and method of manufacture using a contact etch stop layer (CESL) breakthrough process
Semiconductor devices and methods of manufacture are described herein. A method includes forming an opening through an interlayer dielectric (ILD) layer to expose a contact etch stop layer (CESL) disposed over a conductive feature in a metallization layer. The opening is formed using photo sensitive materials, lithographic techniques, and a dry etch process that stops on the CESL. Once the CESL is exposed, a CESL breakthrough process is performed to extend the opening through the CESL and expose the conductive feature. The CESL breakthrough process is a flexible process with a high selectivity of the CESL to ILD layer. Once the CESL breakthrough process has been performed, a conductive fill material may be deposited to fill or overfill the opening and is then planarized with the ILD layer to form a contact plug over the conductive feature in an intermediate step of forming a semiconductor device.
1. A method comprising:
forming an opening in a dielectric material, the opening exposing a target region of an etch stop layer overlying a conductive feature, the target region having a first etch rate with respect to an etchant;
performing a dopant implantation in the target region to modify the target region to have a second etch rate with respect to the etchant, the second etch rate being greater than the first etch rate; and
performing an etch process to remove a portion of the etch stop layer materials in the target region and to expose the conductive feature.
2. The method of claim 1 , wherein the etch stop layer comprises aluminum oxide.
3. The method of claim 1 , wherein the dopant implantation comprises a physical implantation.
4. The method of claim 3 , wherein the physical implantation uses argon as a source material.
5. The method of claim 1 , wherein the dopant implantation comprises a chemical implantation.
6. The method of claim 5 , wherein the chemical implantation uses fluorine as a source material.
7. The method of claim 1 , wherein the dopant implantation implants dopants in sidewalls of the opening.
8. A method comprising:
depositing an etch stop layer over a metallization layer in a first dielectric layer, the etch stop layer having a first etch rate with respect to a first etchant;
depositing a second dielectric layer over the etch stop layer;
forming a via opening through the second dielectric layer, the via opening exposing the etch stop layer;
performing an ion implantation in the etch stop layer through the opening, the ion implantation modifying the first etch rate to a second etch rate with respect to the first etchant, the second etch rate being greater than the first etch rate; and
performing a removal process with the first etchant after the performing the ion implantation, the metallization layer being exposed through the via opening.
9. The method of claim 8 , wherein the performing the removal process comprises a wet etch.
10. The method of claim 9 , wherein the etch stop layer comprises aluminum oxide (AlO x ), and the first etchant comprises deionized water.
11. The method of claim 8 , wherein the ion implantation implants a chemically neutral ion.
12. The method of claim 11 , wherein the chemically neutral ion is argon.
13. The method of claim 8 , wherein the ion implantation implants a chemically reactive ion.
14. The method of claim 13 , wherein the chemically reactive ion comprises fluorine.
15. A method of manufacturing a semiconductor device, the method comprising:
forming a metallization layer over a semiconductor substrate;
forming an etch stop layer over the metallization layer;
forming an interlayer dielectric layer over the etch stop layer, wherein the interlayer dielectric layer has a first thickness; and
forming a metal plug through the interlayer dielectric layer and through the etch stop layer, wherein a dopant implant region is located within the interlayer dielectric layer and located adjacent to a first surface of the interlayer dielectric layer and also adjacent to a second surface of the interlayer dielectric layer, the first surface being in physical contact with the metal plug and the second surface being located on an opposite side of the interlayer dielectric layer than the etch stop layer, wherein the dopant implant region has a second thickness extending from the first surface and a third thickness extending from the second surface, the third thickness being smaller than the first thickness.
16. The method of claim 15 , wherein the forming the metal plug forms the metal plug to extend between the dopant implant region and the metallization layer in a direction perpendicular with a major surface of the semiconductor substrate.
17. The method of claim 16 , wherein after the forming the interlayer dielectric layer the interlayer dielectric layer has a sidewall that is aligned with a sidewall of the etch stop layer.
18. The method of claim 15 , wherein the dopant implant region comprises argon.
19. The method of claim 15 , wherein the dopant implant region comprises fluorine.
20. The method of claim 15 , wherein the forming the etch stop layer forms aluminum oxide.